Transformation: nanotechnology—challenges in transistor design and future technologies

More than 200 years ago the origin of electricity was analyzed for the first time and throughout this process the way to more revolutionary technological inventions has always been enabled by an enhanced insight into the physical process of electric charge manipulation. Although many inventions and patents were considered fundamental research and initially ignored by industry, they have eventually changed our way of living and as such are of enormous economic importance. A rather prominent example in this regard is the transistor, which is one of the key inventions of modern society arguably comparable to the domestication of fire and the invention of the wheel.

As a result of basic research on the physics of solids, transistors were able to replace vacuum tubes in the 1950s, which led in the following to the development of the integrated circuit and the microprocessor, which are at the heart of modern electronics. Thus, transistors paved the way for a new generation of powerful and efficient electronic devices with a seemingly unlimited number of applications in everyday life. As a consequence of the continuous improvement of their performance, modern technologies have enabled numerous innovative ways of global networking by connecting things and people, optimizing work flows as well as saving valuable resources.

The economic importance of these new technologies and the pressure to keep production costs low have been the driving forces for the development and improvement of the transistor. Moore predicted in 1965 an exponential relationship between device complexity (number of transistors per area unit) and time, by stating that “the complexity will double annually.” This prediction has in the meantime been revised to a doubling every two years [1], resulting in over 5 billion transistors being processed on a single chip today. As a consequence of the complexity increase, transistors have been downscaled to the deca-nanometer regime during the past decades, which has resulted in severe reliability issues, power loss and instabilities as the physical limits are approached. Thus, new materials and geometries are required to overcome these challenges.

The new approaches in transistor design have led to the transformation from the field of Microelectronics to the field of Nanoelectronics, where Nanotechnology naturally plays a major role. Here we give a short overview of the consequences that have resulted from downscaling and recent developments in transistor technology together with their challenges.

In digital circuits, the metal-oxide-semiconductor field-effect transistor (MOSFET) is the most important transistor technology due to the achievable short switching times and the nearly loss-less control at low frequencies. In a very simplified way, a transistor can be compared to a switch realized by modifying the conductivity properties of semiconductors (e.g., Si). For a more detailed explanation, Fig. 1 shows the cross section of an \(n\)-type MOSFET containing two highly \(n\)-doped regions, source and drain, separated by a \(p\)-doped body region. An insulating layer (e.g. silicon oxynitride SiON) is sandwiched between the gate and the body, separating them from each other and thus preventing a current flow. Given that a positive supply voltage (\(V_{\mathrm{DD}}\)) is applied between the drain and the source (\(V_{\mathrm{D}}\)), the voltage applied between the gate and the bulk (\(V_{\mathrm{G}}\)) controls the current flow between the drain and the source \(I_{\mathrm{D}}\). If \(V_{\mathrm{G}}=0\) V, the MOSFET is in its off-state and current flow is inhibited because of the reverse biased \(p{-}n\) junction. By applying a low positive \(V_{\mathrm{G}}\) the majority carriers are forced away from the oxide/body interface and therefore a depletion layer near the interface forms which is populated by minority carriers. As soon as \(V_{\mathrm{G}}\) exceeds a certain threshold voltage \(V_{\mathrm {th}}\), the concentration of minority carriers is high enough to form a thin inversion layer near the interface. As a consequence, the minority charge carriers flow freely between the source and drain and the gate voltage controls the carrier concentration in the channel and thus the resistance. Further increase of \(V_{\mathrm{G}}\) results in an increase of \(I_{\mathrm{D}}\) until \(I_{\mathrm{D}}\) reaches the saturation region which corresponds to the on-state of the MOSFET.

Unfortunately, any real device differs from such an ideal switch. The real switching characteristics, as shown in Fig. 2, are typically characterized by four parameters determined by materials, doping and geometry: the off-current, the subthreshold swing \(SS\) (reciprocal value of the slope \(S\) in a log-lin plot), \(V_{\mathrm {th}}\) and the on-current. The off-current (\(I_{\mathrm{D}}\neq 0\) A at \(V_{ \mathrm{G}}=0\) V) is caused by leakage currents between source and drain and is inevitable. Furthermore, the switching process between off- and on-state shows switching dynamics characterized by \(V_{\mathrm {th}}\) and \(SS\) which are limited to certain minimum values, and the on-current is the current flowing through the channel when the MOSFET is in its on-state.

The parameters mentioned in the previous paragraph have to meet certain requirements in digital circuits in order to ensure a correct interaction with other circuit components and a low power consumption of the circuit. A correct interaction assumes that the off-current and the on-current of a MOSFET correspond to output voltages fulfilling the limits for the digital levels low and high, respectively. In the CMOS technology, the digital low level is defined as a voltage between 0 V and 1/\(3V_{\mathrm{DD}}\) and the digital high level is defined as a voltage between 2/\(3V_{\mathrm{DD}}\) and \(V_{\mathrm{DD}}\). Meeting the requirement of clearly distinguishable output voltage levels for the two digital states results in limitations for the ratio between on- and off-current which has to be made as large as possible. This can be achieved by maximizing \(V_{\mathrm{DD}}\) while simultaneously keeping \(SS\) and \(V_{\mathrm {th}}\) as low as possible. Besides increasing the ratio, a high \(V_{\mathrm{DD}}\) would also ensure an on-current which is high enough to drive subsequent digital stages, and low \(SS\) and \(V_{\mathrm {th}}\) would enhance the switching dynamics. However, increasing \(V_{\mathrm{DD}}\) conflicts with the requirement of low power consumption since \(P \propto V_{\mathrm{DD}}^{2}\) and, as mentioned in the previous paragraph, \(SS\) and \(V_{\mathrm {th}}\) are either fundamental limits or limited due to materials, doping and geometry of the MOSFET.

The consideration of these aspects in the fabrication process provide fundamental challenges for the design of MOSFETs in general. Furthermore, excessive scaling of the MOSFET geometries has led to further limitations as discussed in the next section.

While decades ago transistor structures were processed in the micrometer range, modern MOSFET structures have been scaled down to 22 nm in 2008 and to 14 nm in the current generation of transistors. In addition to the scaling of the width (\(W\)) and length (\(L\)) of the transistors, the oxide thickness (\(t_{\mathrm{ox}}\)) has also been scaled down, reaching values less than 2 nm. Considering SiO\(_{\mathrm{2}}\) as the insulating material, 2 nm in fact contain a rather small number layers of atoms as shown in Fig. 3.

The scaling of the geometry results in several design and fabrication challenges, for example, a short transistor length (less than 100 nm) leads to short-channel effects, e.g., drain-induced barrier lowering, which affects the MOSFET performance. Additionally, channel leakage currents are more pronounced, therefore, the off-current increases significantly. Moreover, considering that \(C_{\mathrm{ox}} \propto A\)/\(t _{\mathrm{ox}}\), where \(A=L \times W\) is the area, \(t_{\mathrm{ox}}\) has to be scaled in the same manner as \(A\). Otherwise, \(C_{\mathrm{ox}}\) would increase significantly which would have a great impact on \(V_{\mathrm {th}}\) and the switching dynamics. However, \(t_{\mathrm{ox}}\) is limited to a certain minimum value because of quantum effects like tunneling, leading to a dramatic increase of leakage currents if the oxide thickness is further reduced. With a \(t_{\mathrm{ox}}\) below this value, a loss-less control cannot be ensured any longer. Furthermore, the supply voltages cannot be scaled in the same manner as the device geometry, otherwise, the ratio between the on- and off-current would deteriorate. Last but not least, the electric field in the oxide \(E_{\mathrm{ox}}\) has increased considerably due to the indirect proportionality to \(t_{\mathrm{ox}}\). As a consequence, degradation effects depending on \(E_{\mathrm{ox}}\), e.g., the bias temperature instability have a greater impact than in devices with thicker oxides.

Another consequence of downscaling is a higher variability due to the variance of parameters between MOSFETs processed in the same manner. The variance is higher for nanoscale devices than for large devices in the micrometer range because nanoscale devices contain, in contrast to large devices, only a countable number of discrete dopants. The slightest deviations of their number or position influence the non-uniformly current flow over the width, the so-called percolation path (see Fig. 4 left) [4, 5]. Furthermore, the relative change of device dimensions due to fabrication variability increases with scaling. As a result of both, the variance of discrete dopants and dimension deviations, even MOSFETs of the same technology and processed in the same manner show a significant variance in their characteristics, like \(V_{\mathrm {th}}\), and behave differently in digital circuits.

Even more dramatic, in contrast to Fig. 3, which shows an ideal arrangement of atoms making up a transistor, in reality the atoms are not perfectly arranged. On the one hand, if the oxide material is amorphous, structural defects related to dangling bonds inevitably occur at the bulk/oxide interface and on the other hand, the oxide contains intrinsic defects. Some of these defects have the ability to capture and emit single charge carriers from the conducting channel, disrupting the electrostatics and characteristics of the device. Due to the comparatively large amount of charge carriers in the channel, in large devices, a single capture or emission event has a small impact on the MOSFET parameters. In stark contrast, in nanoscale MOSFETs, such events affect device performance severely [6‐8]. Depending on the position of the defect, the percolation path is disturbed as can be seen in the center and right panels of Fig. 4. This causes a \(V_{\mathrm {th}}\) shift, a degradation of the subthreshold slope and a reduction of the on-current as summarized in Fig. 5. Even one single active defect may shift \(V_{\mathrm {th}}\) by a detrimental value, thus, change the transistors behavior and dynamics in digital circuits dramatically. Such a shift of transistor characteristics can endanger the correct interaction with other components, which makes the circuit less reliable and more likely to fail.

In order to understand the root cause of degradation mechanisms, a large effort has been put into studying single defects related to the failure of devices. Figure 6 shows the recently proposed non-radiative multi-phonon model for one particular defect configuration in the oxide including its interplay with hydrogen [10]. The latter has to be considered since hydrogen is the most abundant element, very reactive and everywhere in the MOSFET due to processing steps like forming gas annealing. The interplay between hydrogen, charge carriers and the particular atomic configuration of the defect can be summarized as a number of clearly discernible configurations (states) [6, 9]. Depending on the position of its energy level within the band gap and its particular properties, an active defect can capture or emit charge carriers which can be described by transitions between four states. However, due to movement of or reaction with hydrogen, the defect can also be deactivated or transformed to a precursor state, both of which being neutral and not contributing to MOSFET parameter changes under operating conditions.

The deep understanding of degradation mechanisms in conventional MOSFETs is one basis for new approaches in transistor design. For example, by using different materials and designs than in CMOS technologies the root cause for degradation mechanisms like interface defects can be avoided and a profound development of future electronic circuits can meet the challenges posed by limits due to fundamental physics of solids.

Recently, researchers in industry and academia have put an effort in finding new geometries and materials that will help in overcoming the challenges due to downscaling. Already in mass production, for example, non-planar multi-gate field-effect transistors (FinFETs) have a cleverly designed gate structure shown in Fig. 7; in contrast to planar devices, the gate is wrapped around the channel instead of being processed on top of it. This allows for a better electrostatic control over the channel, a reduction of the channel leakage current and a decrease of the switching time, making them also appropriate for use in memory cells. Additionally, high-k (high relative permittivity \(\kappa \), also \(\epsilon_{\mathrm{r}}\)) materials, e.g., hafnium oxide (HfO\(_{\mathrm{2}}\)) are used instead of SiO\(_{\mathrm{2}}\), which only has a relatively small permittivity and thus has to be very thin for good electrostatic control over the channel [11, 12]. Due to the fact that \(C_{ \mathrm{ox}}\propto \kappa \)/\(t_{\mathrm{ox}}\), an increase of \(\kappa \) allows an increase of \(t_{\mathrm{ox}}\) without changing the capacitance. At the same time \(E_{\mathrm{ox}}\propto 1\)/\(t_{ \mathrm{ox}}\), and thus an increase of \(t_{\mathrm{ox}}\) makes challenges associated with high \(E_{\mathrm{ox}}\) less severe.

Nevertheless, even with these improvements, the fundamental physics of solids will limit downscaling of chip structures again soon since ultra-scaled FinFETs suffer from the same detrimental mechanisms like planar MOSFETs [13]. Innovative ideas for future solutions have been suggested, for example the tunnel field-effect transistor (TFET). This transistor technology is based on the quantum mechanical tunneling effect. As shown in Fig. 8, the source and drain terminals are doped of opposite type. At a sufficient gate bias, band-to-band tunneling occurs and electrons from the valence band of the \(p\)-type region tunnel into the conduction band of the intrinsic region which results in a current flow across the device. Taking advantage of this effect opens up new possibilities for transistor design. In principle, transistors using band-to-band tunneling for injecting charge carriers into the channel would reach better subthreshold swings—less than 63 mV/decade of current—leading to significant power savings and allowing for further downscaling. However, the experimental realization of a field-effect transistor with \(SS<63\) mV/decade of current has not been demonstrated so far.

A highly inspiring idea for future transistor technologies is based on the revolutionary discovery of the field-effect in 2D materials as shown in Figs. 9 and 10. Depending on their chemical composition, such 2D layers can have metallic, semiconducting or insulating properties, as has been demonstrated during the last years. One important class of materials are the transistor metal dichalcogenides (TMD). There the molecules are formed by transition metal atoms, e.g., Mo and of chalcogen atoms, e.g., S bound covalently to, e.g., MoS\(_{\mathrm{2}}\) [17]. Hundreds of transition metal atoms and chalcogen atoms combinations are available and each of them shows different properties. One remarkable advantage of TMDs is that transistors can be built by “sticking” together layers with different properties without creating structural defects related to dangling bonds at the interfaces as they occur between crystalline and amorphous materials in conventional CMOS transistors. The reason for this is that adjacent layers of TMDs are weakly held together by van der Waals forces. In contrast to conventional CMOS transistors, where structural defects at the interface strongly affect the performance, degradation caused by such defects does not play a role here. Therefore, this technology might be one innovation towards more reliable transistors even in the several nanometer regimes.

Although approaches for constructing improved transistors have been made, technologies which can enable scaling transistor dimensions to the sub deca-nanometer regime and further are not yet ready for mass production. Reliability issues, power loss, temperature instability and many other detrimental effects have to be eliminated first. Therefore, further research in this field is inevitable and will open the doors towards new approaches for the improvement of digital circuits. These improvements will in a next step enable new applications which are important for many aspects of our lives, such as healthcare, the automotive sector, and security.

The pressure on industry to keep the production costs for high-efficiency electronic devices low has led to an excessive downscaling of the most important part in digital circuits, the MOSFET. As a consequence, the limits of physics have been reached several times during the past two decades which has resulted in severe reliability issues, power loss, and instabilities. Although innovative approaches have been made recently in order to meet some of these issues, an holistic solution which will enable the further increase of complexity in digital circuits has not been introduced yet. However, ideas for new transistor technologies based on other materials and designs than used in CMOS technology have already been suggested and might one day open the door to future applications. With further research, these new technologies can guarantee affordable electronic devices in the future.