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Erschienen in:
Research and Development History of Three-Dimensional Integration Technology Kapitel lesen Erstes Kapitel lesen

2015 | OriginalPaper | Buchkapitel

3. TSV Processes

verfasst von : Masahiko Tanaka, Dr. Makoto Sekine, Itsuko Sakai, Yutaka Kusuda, Tomoyuki Nonaka, Osamu Tsuji, Dr. Kazuo Kondo

Erschienen in: Three-Dimensional Integration of Semiconductors

Verlag: Springer International Publishing

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Abstract

Through-silicon via requires some unique process technologies. This chapter consists of four sub chapters. First sub chapter descibes deep silicon etching by “Bosch process.” The process adopts high aspect ratio and straight via. Some process paramaters are discussed.
Next sub chapter takes up steady-sate silicon etching process, also know as “non-Bosch process.” Physics and chemistry to realize fast and controlled deep silicon etching are discussed.
Third sub chapter deals with low temperature dielectric deposition. Unique liquid source chemical vapor deposition at low temperature and its properties are introduced.
Finally, electrodeposition of copper to fill high aspect ratio via is described. Electrochemical analysis, mathematical models of via filling, high-speed via filling and reduction of thermal expansion coefficient to avoid “copper pop-up” are discussed.

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Vorheriges Kapitel Recent Research and Development Activities of Three-Dimensional Integration Technology
Nächstes Kapitel Wafer Handling and Thinning Processes
Literatur
1.
Laemer FD, Schilp A (1992) A method for anisotropic etching of silicon. German Patent No. DE4241045
2.
Zoschke K, Oppermann H, Manier CA, Ndip I, Puschmann R, Ehrmann O, Wolf J, Lang KD (2012) Wafer level 3D system integration based on silicon interposers with through silicon vias. In: Proceedings of 14th IEEE electronics packaging technology conference 5–7 Dec. 2012, pp 8–13
3.
Mourier T, Ribiere C, Romero G, Gottardi M, Allouti N, Eleouet R, Roman A, Magis T, Minoret S, Ratin C, Scevola D, Dupuy E, Martin B, Gabette L, Marseilhan D, Enot T, Pellat M, Loup V, Segaud R, Feldis H, Charpentier A, Bally JP, Assous M, Charbonnier I, Laviron C, Coudrain P, Sillon N (2913) 3D integration challenges today from technological toolbox to industrial prototypes. Proceedings of IEEE interconnect technology conference, pp 1–3
4.
Sheu SS, Lin ZH, Lin CS, Lau JH, Lee SH, Su KL, Ku TK, Wu SH, Hung JF, Chen PS, Lai SJ, Lo WC, Kao MJ (2012) Electrical characterization of through silicon vias (TSVs) with an on chip bus driver for 3D IC integration. Proceedings of IEEE 62nd electrical components and technology conference, pp 851–856
5.
Peterson K (1982) Silicon as a mechanical material. Proc IEEE 70(5):420–457CrossRef
6.
Bhardwaj JK, Ashraf H, Hopkins J, Johnston I, McAuley S, Hall S, Nicholls G, Atabo L, Hynes A, Welch C, Barker A, Gunn B, Lea L, Guibarra E, Watcham S (1999) Advances in high rate silicon and oxide etching using ICP. MEMS/MST technology symposium at SEMICON West’99, San Francisco, CA, USA. July 12–16, 1999
7.
Hynes AM, Ashraf H, Bhardwaj JK, Hopkins J, Johnston I, Shepherd JN (1999) Recent advances in silicon etching for MEMS using the ASETM process. Sens Actuators 74:13–17CrossRef
8.
Pang SW (2001) Dry processing of high aspect ratio Si microstructures for MEMS. Proceedings of international symposium on dry process, pp 49–55
9.
Hashimoto K (1994) Charge damage caused by electron shading effect. Jpn J Appl Phys 33(10):6013–6018CrossRef
10.
Bhardwaj JK, Ashraf H, Khamsehpour B, Hopkins J, Hynes AM, Ryan ME, Haynes DM (2000) Method of surface treatment of semiconductor substrates. US Patent No. 6,051,503
11.
Hartig MJ, Arnold JC (1997) Inductively coupled plasma reactor and process. US Patent No. US 5,683,548 A
12.
Fukushima T, Bea J, Murugesan M, Lee KW, Koyanagi M (2013) Development of via-last 3D integration technologies using a new temporary adhesive system. 3D systems integration conference (3DIC), San Francisco, 2–4 Oct 2013, pp 1–4
13.
Laermer F, Schilp A (1996) Method of anisotropically etching silicon. US Patent, 5501893
14.
Ayón AA, Braff R, Lin CC, Sawin HH, Schmidt and MA (1999) Characterization of a time multiplexed inductively coupled plasma etcher. J Electrochem Soc 146(1):339–349CrossRef
15.
Tachi S, Tsujimoto K, Okudaira S (1988) Low-temperature reactive ion etching and microwave plasma etching of silicon. Appl Phys Lett 52(8):616CrossRef
16.
Pruessner MW, Rabinovich WS, Stivater TH, Park D, Baldwin JW (2007) Cryogenic etch process development for profile control of high aspect-ratio submicron silicon trenches. J Vac Sci Technol B25(1):21CrossRef
17.
Sakai I, Sasaki K, Tomioka K, Ohiwa T, Sekine M, Mimura T, Nagaseki K (2001) Proceedings of the 1st international symposium on dry process. The institute of electrical engineers of Japan, Tokyo, p 57
18.
Sakai I, Sakurai N, Ohiwa T (2008) Proceedings of the international symposium on dry process, The Japan society of applied physics, Tokyo, p 125
19.
Horiike Y, Okano H, Yamazaki T, Horie H (1981) High-rate reactive ion etching of SiO2 using a magnetron discharge. Jpn J Appl Phys Part 2 20(11):L817
20.
Hill ML, Hinson DC (1985) Advantages of Magnetron Etching. Solid State Technol 28:243
21.
Kinoshita H, Ishida T, Ohno S (1986) Proceedings of the symposium on dry process. The institute of electrical engineers of Japan, Tokyo, p 36
22.
Müller P, Heinrich F, Mader H (1989) Magnetically enhanced reactive ion etching (MERIE) with different field configurations. Microelectron Eng 10(1):55–67CrossRef
23.
Sekine M, Narita M, Horioka K, Yoshida Y, Okano H (1995) A new high-density plasma etching system using A dipole-ring magnet. Jpn J Appl Phys 34(11):6274CrossRef
24.
d’Agostino R, Flamm D (1981) Plasma etching of Si and SiO2 in SF6-O2 mixtures. J Appl Phys 52(1):162CrossRef
25.
Gomez S, Belen RJ, Kiehlbauch M, Aydil ES (2004) Etching of high aspect ratio structures in Si using SF6/O2 plasma. J Vac Sci Technol A22(3):606CrossRef
26.
Shimizu H, Kimura D, Komiya H, Kawabata R (1984) Proceedings of the symposium on dry process. The institute of electrical engineers of Japan, Tokyo, p 121
27.
Coburn JW, Chen M (1980) Optical emission spectroscopy of reactive plasmas: A method for correlating emission intensities to reactive particle density. J Appl Phys 51(6):3134CrossRef
28.
Amasaki S, Takeuchi T, Takeda K, Ishikawa K, Kondo H, Sekine M, Hori M, Sakurai N, Hayashi H, Sakai I, Ohiwa T (2010) Proceedings of the international symposium on dry process. The Japan society of applied physics, Tokyo, p 97
29.
Amasaki S, Takeuchi T, Takeda K, Ishikawa K, Kondo H, Sekine M, Hori M, Sakurai N, Hayashi H, Sakai I, Ohiwa T Proceedings of the international symposium on dry process. The Japan society of applied physics, Tokyo, p 33
30.
Nagai H, Hiramatsu M, Hori M, Goto T (2003) Measurement of oxygen atom density employing vacuum ultraviolet absorption spectroscopy with microdischarge hollow cathode lamp. Rev Sci Instrum 74(7):3453CrossRef
31.
Booth JP, Joubert O, Pelletier J, Sadeghi N (1991) Oxygen atom actinometry reinvestigated: comparison with absolute measurements by resonance absorption at 130 nm. J Appl Phys 69(2):618CrossRef
32.
Pereora J, Pichon L, Dussart R, Cardinaud C, Duluard CY, Oubensaid EH, Lefaucheux P, Boufnichel M, Ranson P (2009) In situ x-ray photoelectron spectroscopy analysis of SiOxFy passivation layer obtained in a SF6/O2 cryoetching process. Appl Phys Lett 94:071501CrossRef
33.
Flamm DL, Donnelly VM, Mucha JA (1981) The reaction of fluorine atoms with silicon. J Appl Phys 52(5):3633CrossRef
34.
Lieberman MA, Lichtenberg AJ (2004) Principles of plasma discharges and materials processing, 2nd ed., p 587
35.
Kusuda Y, Nonaka T, Motoyama S (2013) TSV process using DRIE and cathode coupled PECVD. ECS Trans 50(32):3–9CrossRef
36.
Kusuda Y, Minaguchi T, Miyashita T, Motoyama S (2009) Sidewall insulator film deposition for the TSV process using cathode coupled PECVD. The 9th international workshop on microelectronics assembling and packaging, p 41, Fukuoka, Japan
37.
Hiramoto M, Minaguchi T, Motoyama S (2007) Deposition of SiO2 film with excellent step coverage using PECVD. Mater Stage 7(5):16–20 (in Japanese)
38.
SAMCO Inc. (2004) PECVD systems for optical devices—ST series. Opto devices technology outlook. Electr J 28:287–289 (in Japanese)
39.
Laemer FD, Schilp A (1994) A method for anisotropic etching of silicon, German Patent No. DE4241045 C1, May 26
40.
Nonaka T, Oda H, Noda Y, Kuratomi N, Nakano H (2012) A study of via hole etching for TSV process. The 11th APCPST abstract. Kyoto University, Kyoto, Japan, p 286
41.
Andoricacos PC, Uzoh C et al (1998) IBM J Res Devel 42:567–572
42.
Moffat TP, Wheeler D et al (2001) Electrochem Solid-State Lett 4:C26–C29
43.
West AC, Mayer S et al (2001) Electrochem Solid-State Lett 4:C50–C53
44.
Tantavishet N, Pritzker M et al (2003) J Electrochem Soc 150:C665–C669
45.
Kondo K, Matsumoto T et al (2004) J Electrochem Soc 151:C250–C256
46.
White JR (1987) J Appl Electrochem 17:977–1003
47.
Nagy Z, Blaudeau JP (1995) J Electrochem Soc 142:L87–L92
48.
Kondo K, Hamazaki K (2014) ECS Electrochem Lett 3(4):D3–D5
49.
Kondo K, Nakamura T (2009) J Appl Electrochem 39:1789–1794
50.
Kondo K, Yonezawa T et al (2005) J Electrochem Soc 152(11):H173–H177
51.
Sun J-J, Kondo K et al (2003) J Electrochem Soc 150(6):G355–G358
52.
Kondo K, Suzuki Y et al (2010) Electrochem S-S Lett. 13(5):D26–D28
53.
Hayashi T, Kondo K et al (2011) J Electrochem Soc 158(12):D715–D718
54.
Akolkar R (2013) ECS Electrochem Lett 2(2):D5–D9
55.
Hayashi T, Kondo K (2013) J Electrochem Soc 160(6):D256–D259
56.
Luhn O, Radisic A et al (2009) Electrochem & S-S Lett 12(5):D39–D41
57.
Luhn O, Van Hoof C et al (2009) Electrochim Acta 54:2504–2508
58.
Radisic A, Luhn O et al. (2011) Microelectronic Eng 88:701–704
59.
Kadota H et al. (2010) JIEP 13(3):213–219 (in Japanese)
60.
Moffat TP, Josell D (2012) J Electrochem Soc 159(4):D208–D216
61.
Beica R, Sharbono C (2008) Through silicon via copper electrodeposition for 3D integration. Proceedings of ECTC conference
62.
Baskaran R, McHugh P (2011) Characterization of the organic components in a commercial TSV filling chemistry. Paper presented at the 220th meeting of the Electrochemical Society, Oct 2011
63.
Flugel A, Amold M (2011) Tailored design of suppressor ensembles for damascene and 3D-TSV copper plating. Paper presented at the 220th meeting of the electrochemical society, Oct 2011
64.
Arnold M, Emnet C (2010) New concept for advanced 3D TSV copper plating additives. Paper presented at the 218th meeting of the electrochemical society, Oct 2011
65.
Adolf JD, Landau U (2009) Scaling analysis of bottom up fill with application to through silicon via. Paper presented at the 216th meeting of the electrochemical society, Oct 2009
66.
Landau U (2010) Electroplating of interconnects—scaling from nanoscale dual-damascene to micron-scale through silicon vias. Paper presented at the 218th meeting of the electrochemical society, Oct 2010
67.
Adolf JD, Landau U (2010) Additive adsorption and transport effects on the void-free metallization of through silicon vias. Paper presented at the 218th meeting of the electrochemical society, Oct 2010
68.
Adolf JD, Landau U (2011) Leveler effects on filling of through silicon vias. Paper presented at the 220th meeting of the electrochemical society, Oct 2011
69.
Che FX, Putra W et al (2011) Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV). In: Proceedings of 3DIC 2011, 2011
70.
Kumar N et al (2011) Advanced reliability study of TSV interposers and interconnects for the 28 nm technology FPGA. Proceedings of ECTC 2011
71.
Huyghebaerta C, Coenena J et al (2011) Microelectr Eng 88:745–748 (5th May)
72.
Croesa K, Varela O et al (2011) Microelectronics reliability 51 (9–11):1856–1859
73.
Metadaten
Titel
TSV Processes
verfasst von
Masahiko Tanaka
Dr. Makoto Sekine
Itsuko Sakai
Yutaka Kusuda
Tomoyuki Nonaka
Osamu Tsuji
Dr. Kazuo Kondo
Copyright-Jahr
2015
Buch
Three-Dimensional Integration of Semiconductors

Print ISBN: 978-3-319-18674-0

Electronic ISBN: 978-3-319-18675-7

Copyright-Jahr: 2015

DOI
https://doi.org/10.1007/978-3-319-18675-7_3

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