1. Understanding Ageing Mechanisms

This chapter starts with a brief review on the basic ageing phenomenon and the working principles and structures of MOSFET transistors. It then presents the unwanted but unavoidable oxide defects leading to charge traps and presents activation mechanisms. These defects can lead to a variety of known ageing effects, such as negative/positive bias instability, hot carrier degradation (alias hot carrier injection), random telegraph noise and time-dependent dielectric breakdown. The impact of these effects onto the individual transistor and consequentially the entire integrated circuit are then discussed. The remainder of this chapter reviews various quantitative ageing models. It starts with the fundamental explicit switching trap models, which individually describe each of the many traps inside every transistor oxide layer. The more abstract stochastic trap representation as capture-emission time maps is leading to practical models at the TCAD and electrical level, respectively. Based on these fundamental models, there are various further abstractions, bridging the gap between the nanosecond timescales, integrated circuits work at and the years or decades, over which circuit ageing is taking place. Analytic models offer a simple ageing assessment by making several worst-case assumptions, usually leading to a vast overestimation. CET map abstractions allow a realistic assessment of the ageing of small circuits such as individual critical paths. Finally, trap centric models enable several ways of accelerating ageing models. The most sophisticated ones can process millions of transistors over years of lifetime with a reasonable accuracy.