2011 | OriginalPaper | Buchkapitel
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits
verfasst von : Takumi Okuhira, Tohru Ishihara
Erschienen in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
Verlag: Springer Berlin Heidelberg
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Since the clocking power consumption in today’s processors is considerably large, reducing the clocking power consumption contributes to the reduction of the total power consumption in the processors. Recently, a gated flip-flop is proposed for reducing the clocking power consumption of flip-flop circuits. The gated flip-flop employs a clock-gating circuit which cuts off an internal clock signal if the data stored in the flip-flop does not need to be updated. Although this reduces the clocking power consumption, the power dissipated in the clock-gating circuit is still large. For reducing the power dissipated in the clock-gating circuit, this paper proposes a technique for unifying the multiple clock-gating circuits, which reduces the overhead of the clock-gating circuit. Post-layout simulation results obtained using a commercial embedded processor which employs our unified gated flip-flop demonstrate that our technique reduces the power consumption of a core part of the processor by 25% on average and 33% at the best case compared to the same processor with the conventional gated flip-flop.