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Erschienen in:
1999 | OriginalPaper | Buchkapitel
Verification of Finite-State-Machine Refinements Using a Symbolic Methodology
verfasst von : Stefan Hendricx, Luc Claesen
Erschienen in: Correct Hardware Design and Verification Methods
Verlag: Springer Berlin Heidelberg
Enthalten in: Professional Book Archive
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The top-down design of VLSI-systems typically features a step-wise refinement of intermediate solutions. Even though these refinements do usually not preserve time-scales, current formal verification approaches are largely based on the assumption that both specification and implementation utilize the same scales of time. In this paper, a symbolic methodology is presented to verify the step-wise refinement of finite state machines, allowing for possible differences in timing-granularity.