Skip to main content
Erschienen in:
Buchtitelbild

2017 | OriginalPaper | Buchkapitel

1. Virtual Prototyping of Embedded Systems: Speed and Accuracy Tradeoffs

verfasst von : Vania Joloboff, Andreas Gerstlauer

Erschienen in: Cyber-Physical System Design from an Architecture Analysis Viewpoint

Verlag: Springer Singapore

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Virtual prototyping has emerged as an important technique for the development of devices combining hardware and software, in particular for the development of embedded computer components integrated into larger cyber-physical systems with stringent performance, safety or security requirements. Because virtual prototypes allow for observing and testing the system without requiring a real hardware at hand, they make it possible to test application software and use formal methods tools to validate the system properties at early design stages. A virtual prototype is an abstraction that emulates, with more or less accuracy, the real system under design. That emulation is usually significantly slower than the real application. In this survey, we overview different virtual prototyping techniques that can be used, and the compromises that they may offer to trade-off some aspects of reality in exchange for other higher priority objectives of the project.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat G. Arnout, SystemC standard, in Proceedings of the Asia South Pacific Design Automation Conference, ASPDAC (2000), pp. 573–578 G. Arnout, SystemC standard, in Proceedings of the Asia South Pacific Design Automation Conference, ASPDAC (2000), pp. 573–578
2.
Zurück zum Zitat F. Bellard, QEMU, a fast and portable dynamic translator, in Proceedings of the USENIX Annual Technical Conference, ATEC (2005), p. 41 F. Bellard, QEMU, a fast and portable dynamic translator, in Proceedings of the USENIX Annual Technical Conference, ATEC (2005), p. 41
3.
Zurück zum Zitat E. Berg, H. Zeffer, E. Hagersten, A statistical multiprocessor cache model, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS (2006), pp. 89–99 E. Berg, H. Zeffer, E. Hagersten, A statistical multiprocessor cache model, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS (2006), pp. 89–99
4.
Zurück zum Zitat A. Bouchhima, P. Gerin, F. Pétrot, Automatic instrumentation of embedded software for high level hardware/software co-simulation. in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2009), pp. 546–551 A. Bouchhima, P. Gerin, F. Pétrot, Automatic instrumentation of embedded software for high level hardware/software co-simulation. in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2009), pp. 546–551
5.
Zurück zum Zitat F. Brandner, A. Fellnhofer, A. Krall, D. Riegler, Fast and accurate simulation using the LLVM compiler framework, in Methods and Tools, Rapid Simulation and Performance Evaluation, RAPIDO (2009) F. Brandner, A. Fellnhofer, A. Krall, D. Riegler, Fast and accurate simulation using the LLVM compiler framework, in Methods and Tools, Rapid Simulation and Performance Evaluation, RAPIDO (2009)
6.
Zurück zum Zitat O. Bringmann, W. Ecker, A. Gerstlauer, A. Goyal, D. Mueller-Gritschneder, P. Sasidharan, S. Sing, The next generation of virtual prototyping: ulta-fast yet accurate simulation of HW/SW systems, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2015) O. Bringmann, W. Ecker, A. Gerstlauer, A. Goyal, D. Mueller-Gritschneder, P. Sasidharan, S. Sing, The next generation of virtual prototyping: ulta-fast yet accurate simulation of HW/SW systems, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2015)
7.
Zurück zum Zitat D. Burger, T. Austin, D. Burger, T.M. Austin, The simplescalar tool set, version 2.0. Technical Report TR-1342 (University of Wisconsin-Madison, 1997) D. Burger, T. Austin, D. Burger, T.M. Austin, The simplescalar tool set, version 2.0. Technical Report TR-1342 (University of Wisconsin-Madison, 1997)
8.
Zurück zum Zitat L. Cai D. Gajski, Transaction level modeling: an overview. in Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis, CODES+ISSS (2003), pp. 19–24 L. Cai D. Gajski, Transaction level modeling: an overview. in Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis, CODES+ISSS (2003), pp. 19–24
9.
Zurück zum Zitat L. Cai, A. Gerstlauer, D. Gajski, Retargetable profiling for rapid, early system-level design space exploration. in Proceedings of the 41st Design Automation Conference, DAC (2004), pp. 281–286 L. Cai, A. Gerstlauer, D. Gajski, Retargetable profiling for rapid, early system-level design space exploration. in Proceedings of the 41st Design Automation Conference, DAC (2004), pp. 281–286
10.
Zurück zum Zitat S. Callanan, D.J. Dean, E. Zadok, Extending GCC with modular GIMPLE optimizations, in Proceedings of the 2007 GCC Developers Summit (2007), pp. 31–37 S. Callanan, D.J. Dean, E. Zadok, Extending GCC with modular GIMPLE optimizations, in Proceedings of the 2007 GCC Developers Summit (2007), pp. 31–37
11.
Zurück zum Zitat S. Chakravarty, Z. Zhao, A. Gerstlauer, Automated, retargetable back-annotation for host compiled performance and power modeling, in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2013) S. Chakravarty, Z. Zhao, A. Gerstlauer, Automated, retargetable back-annotation for host compiled performance and power modeling, in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2013)
12.
Zurück zum Zitat D. Chiou, D. Sunwoo, J. Kim, N. Patil, W.H. Reinhart, D.E. Johnson, Z. Xu, The FAST methodology for high-speed SoC/computer simulation, in Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD (2007), pp. 295–302 D. Chiou, D. Sunwoo, J. Kim, N. Patil, W.H. Reinhart, D.E. Johnson, Z. Xu, The FAST methodology for high-speed SoC/computer simulation, in Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD (2007), pp. 295–302
13.
Zurück zum Zitat B. Cmelik, D. Keppel, Shade: a fast instruction-set simulator for execution profiling, in Proceedings of the 1994 ACM Conference on Measurement and Modeling of Computer Systems, SIGMETRICS (May 1994), pp. 128–137 B. Cmelik, D. Keppel, Shade: a fast instruction-set simulator for execution profiling, in Proceedings of the 1994 ACM Conference on Measurement and Modeling of Computer Systems, SIGMETRICS (May 1994), pp. 128–137
15.
Zurück zum Zitat L.P. Deutsch, A.M. Schiffman, Efficient implementation of the Smalltalk-80 system. in Proceedings of the 11th ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages, POPL (1984), pp. 297–302 L.P. Deutsch, A.M. Schiffman, Efficient implementation of the Smalltalk-80 system. in Proceedings of the 11th ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages, POPL (1984), pp. 297–302
16.
Zurück zum Zitat A. Donlin, Transaction level modeling: flows and use models, in Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2004), pp. 75–80 A. Donlin, Transaction level modeling: flows and use models, in Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2004), pp. 75–80
17.
Zurück zum Zitat A. Faravelon, N. Fournel, F. Ptrot, Fast and accurate branch predictor simulation, in Proceedings of the Design Automation and Test in Europe Conference, DATE (2015), pp. 317–320 A. Faravelon, N. Fournel, F. Ptrot, Fast and accurate branch predictor simulation, in Proceedings of the Design Automation and Test in Europe Conference, DATE (2015), pp. 317–320
18.
Zurück zum Zitat A. Fauth, J. Van Praet, M. Freericks, Describing instruction set processors using nML, in Proceedings of the 1995 European Conference on Design and Test, EDTC (1995), p. 503 A. Fauth, J. Van Praet, M. Freericks, Describing instruction set processors using nML, in Proceedings of the 1995 European Conference on Design and Test, EDTC (1995), p. 503
19.
Zurück zum Zitat Y. Futamura, Partial evaluation of computation process-an approach to a compiler-compiler. High. Order Symbolic Comput. 12(4), 381–391 (1999)CrossRefMATH Y. Futamura, Partial evaluation of computation process-an approach to a compiler-compiler. High. Order Symbolic Comput. 12(4), 381–391 (1999)CrossRefMATH
20.
Zurück zum Zitat L. Gao, K. Karuri, S. Kraemer, R. Leupers, G. Ascheid, H. Meyr, Multiprocessor performance estimation using hybrid simulation, in Proceedings of the Design Automation Conference, DAC (2008), pp. 325–330 L. Gao, K. Karuri, S. Kraemer, R. Leupers, G. Ascheid, H. Meyr, Multiprocessor performance estimation using hybrid simulation, in Proceedings of the Design Automation Conference, DAC (2008), pp. 325–330
21.
Zurück zum Zitat P. Gerin, H. Shen, A. Chureau, A. Bouchhima, A. Jerraya, Flexible and executable hardware/software interface modeling for multiprocessor SoC design using SystemC, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2007) P. Gerin, H. Shen, A. Chureau, A. Bouchhima, A. Jerraya, Flexible and executable hardware/software interface modeling for multiprocessor SoC design using SystemC, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2007)
22.
Zurück zum Zitat A. Gerstlauer, S. Chakravarty, M. Kathuria, P. Razaghi, Abstract system-level models for early performance and power exploration, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2012), pp. 213–218 A. Gerstlauer, S. Chakravarty, M. Kathuria, P. Razaghi, Abstract system-level models for early performance and power exploration, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2012), pp. 213–218
23.
Zurück zum Zitat A. Gerstlauer, H. Yu, D. Gajski, RTOS modeling for system level design, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2003), pp. 130–135 A. Gerstlauer, H. Yu, D. Gajski, RTOS modeling for system level design, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2003), pp. 130–135
24.
Zurück zum Zitat F. Ghenassia (ed.), Transaction-Level Modeling with SystemC. TLM Concepts and Applications for Embedded Systems (Springer, New York, 2005). ISBN 0-387-26232-6 F. Ghenassia (ed.), Transaction-Level Modeling with SystemC. TLM Concepts and Applications for Embedded Systems (Springer, New York, 2005). ISBN 0-387-26232-6
25.
Zurück zum Zitat M. Gligor, N. Fournel, F. Pétrot, Using binary translation in event driven simulation for fast and flexible MPSoC simulation, in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2009), pp. 71–80 M. Gligor, N. Fournel, F. Pétrot, Using binary translation in event driven simulation for fast and flexible MPSoC simulation, in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2009), pp. 71–80
26.
Zurück zum Zitat G. Hadjiyiannis, S. Hanono, S. Devadas, ISDL: an instruction set description language for retargetability and architecture exploration. Des. Autom. Embed. Syst. 6(1), 39–69 (2000)CrossRefMATH G. Hadjiyiannis, S. Hanono, S. Devadas, ISDL: an instruction set description language for retargetability and architecture exploration. Des. Autom. Embed. Syst. 6(1), 39–69 (2000)CrossRefMATH
27.
Zurück zum Zitat G. Hamerly, E. Perelman, B. Calder, How to use SimPoint to pick simulation points. SIGMETRICS Perform. Eval. Rev. 31(4), 25–30 (2004)CrossRef G. Hamerly, E. Perelman, B. Calder, How to use SimPoint to pick simulation points. SIGMETRICS Perform. Eval. Rev. 31(4), 25–30 (2004)CrossRef
28.
Zurück zum Zitat N. Hardavellas, S. Somogyi, T.F. Wenisch, R.E. Wunderlich, S. Chen, J. Kim, B. Falsafi, J.C. Hoe, A.G. Nowatzyk, SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Perform. Eval. Rev. 31(4), 31–34 (2004)CrossRef N. Hardavellas, S. Somogyi, T.F. Wenisch, R.E. Wunderlich, S. Chen, J. Kim, B. Falsafi, J.C. Hoe, A.G. Nowatzyk, SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Perform. Eval. Rev. 31(4), 31–34 (2004)CrossRef
29.
Zurück zum Zitat M.R. Hartoog, J.A. Rowson, P.D. Reddy, S. Desai, D.D. Dunlop, E.A. Harcourt, N. Khullar, Generation of software tools from processor descriptions for hardware/software codesign, in Proceedings of the 34th Annual Design Automation Conference, DAC (1997), pp. 303–306 M.R. Hartoog, J.A. Rowson, P.D. Reddy, S. Desai, D.D. Dunlop, E.A. Harcourt, N. Khullar, Generation of software tools from processor descriptions for hardware/software codesign, in Proceedings of the 34th Annual Design Automation Conference, DAC (1997), pp. 303–306
31.
Zurück zum Zitat D.-Y. Hong, C.-C. Hsu, P.-C. Yew, J.-J. Wu, W.-C. Hsu, P. Liu, C.-M. Wang, Y.-C. Chung, HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores, in Proceedings of the Tenth International Symposium on Code Generation and Optimization, CGO (2012), pp. 104–113 D.-Y. Hong, C.-C. Hsu, P.-C. Yew, J.-J. Wu, W.-C. Hsu, P. Liu, C.-M. Wang, Y.-C. Chung, HQEMU: a multi-threaded and retargetable dynamic binary translator on multicores, in Proceedings of the Tenth International Symposium on Code Generation and Optimization, CGO (2012), pp. 104–113
32.
Zurück zum Zitat Y. Hwang, S. Abdi, D. Gajski, Cycle-approximate retargetable performance estimation at the transaction level, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2008), pp. 3–8 Y. Hwang, S. Abdi, D. Gajski, Cycle-approximate retargetable performance estimation at the transaction level, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2008), pp. 3–8
34.
Zurück zum Zitat D. Jefferson, H. Sowizral, Fast concurrent simulation using the time warp mechanism. Technical report, the Rand Corporation (Santa Monica, California, 1982). Rand Note N-1906AF D. Jefferson, H. Sowizral, Fast concurrent simulation using the time warp mechanism. Technical report, the Rand Corporation (Santa Monica, California, 1982). Rand Note N-1906AF
35.
Zurück zum Zitat V. Joloboff, X. Zhou, C. Helmstetter, X. Gao, Fast instruction set simulation using LLVM-based dynamic translation. in International MultiConference of Engineers and Computer Scientists, IAENG vol. 2188 (Springer, 2011), pp. 212–216 V. Joloboff, X. Zhou, C. Helmstetter, X. Gao, Fast instruction set simulation using LLVM-based dynamic translation. in International MultiConference of Engineers and Computer Scientists, IAENG vol. 2188 (Springer, 2011), pp. 212–216
36.
Zurück zum Zitat D. Jones, N. Topham, High speed CPU simulation using LTU dynamic binary translation, in Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC (2009), pp. 50–64 D. Jones, N. Topham, High speed CPU simulation using LTU dynamic binary translation, in Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC (2009), pp. 50–64
37.
Zurück zum Zitat R. Kassem, M. Briday, J.-L. Bchennec, G. Savaton, Y. Trinquet, Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. J. Syst. Archit. 58(8), 318–337 (2012)CrossRef R. Kassem, M. Briday, J.-L. Bchennec, G. Savaton, Y. Trinquet, Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. J. Syst. Archit. 58(8), 318–337 (2012)CrossRef
38.
Zurück zum Zitat T. Kempf, M. Dorper, R. Leupers, G. Ascheid, H. Meyr, T. Kogel, B. Vanthournout, A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2005) T. Kempf, M. Dorper, R. Leupers, G. Ascheid, H. Meyr, T. Kogel, B. Vanthournout, A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2005)
39.
Zurück zum Zitat K. Keutzer, A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, System-level design: orthogonalization of concerns and platform-based design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) 19(12), 1523–1543 (2000)CrossRef K. Keutzer, A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, System-level design: orthogonalization of concerns and platform-based design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) 19(12), 1523–1543 (2000)CrossRef
40.
Zurück zum Zitat M. Krause, D. Englert, O. Bringmann, W. Rosenstiel, Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation, in Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2008), pp. 143–148 M. Krause, D. Englert, O. Bringmann, W. Rosenstiel, Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation, in Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2008), pp. 143–148
41.
Zurück zum Zitat C. Lattner, V. Adve, LLVM: a compilation framework for lifelong program analysis & transformation, in Proceedings of the 2004 International Symposium on Code Generation and Optimization, CGO (2004) C. Lattner, V. Adve, LLVM: a compilation framework for lifelong program analysis & transformation, in Proceedings of the 2004 International Symposium on Code Generation and Optimization, CGO (2004)
42.
Zurück zum Zitat R. Le Moigne, O. Pasquier, J.-P. Calvez, A generic RTOS model for real-time systems simulation with SystemC, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2004) R. Le Moigne, O. Pasquier, J.-P. Calvez, A generic RTOS model for real-time systems simulation with SystemC, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2004)
43.
Zurück zum Zitat D. Lee, L.K. John, A. Gerstlauer, Dynamic power and performance back-annotation for fast and accurate functional hardware simulation, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2015) D. Lee, L.K. John, A. Gerstlauer, Dynamic power and performance back-annotation for fast and accurate functional hardware simulation, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2015)
44.
Zurück zum Zitat D. Lee, T. Kim, K. Han, Y. Hoskote, L.K. John, A. Gerstlauer, Learning-based power modeling of system-level black-box IPs, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD (2015) D. Lee, T. Kim, K. Han, Y. Hoskote, L.K. John, A. Gerstlauer, Learning-based power modeling of system-level black-box IPs, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD (2015)
45.
Zurück zum Zitat R. Leupers, J. Elste, B. Landwehr, Generation of interpretive and compiled instruction set simulators, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (1999), pp. 339–342 R. Leupers, J. Elste, B. Landwehr, Generation of interpretive and compiled instruction set simulators, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (1999), pp. 339–342
46.
Zurück zum Zitat W. Liu, M.C. Huang, EXPERT: expedited simulation exploiting program behavior repetition, in Proceedings of the 18th Annual International Conference on Supercomputing, ICS (2004), pp. 126–135 W. Liu, M.C. Huang, EXPERT: expedited simulation exploiting program behavior repetition, in Proceedings of the 18th Annual International Conference on Supercomputing, ICS (2004), pp. 126–135
47.
Zurück zum Zitat K. Lu, D. Muller-Gritschneder, U. Schlichtmann, Analytical timing estimation for temporally decoupled TLMs considering resource conflicts, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2013), pp. 1161–1166 K. Lu, D. Muller-Gritschneder, U. Schlichtmann, Analytical timing estimation for temporally decoupled TLMs considering resource conflicts, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2013), pp. 1161–1166
48.
Zurück zum Zitat K. Lu, D. Müller-Gritschneder, U. Schlichtmann, Fast cache simulation for host-compiled simulation of embedded software, in Proceedings of the Design, Automation and Test in Europe Conference (2013), pp. 637–642 K. Lu, D. Müller-Gritschneder, U. Schlichtmann, Fast cache simulation for host-compiled simulation of embedded software, in Proceedings of the Design, Automation and Test in Europe Conference (2013), pp. 637–642
49.
Zurück zum Zitat P. Magnusson, B. Werner, Efficient memory simulation in SimICS, in Proceedings of the 28th Annual Simulation Symposium (April 1995), pp. 62–73 P. Magnusson, B. Werner, Efficient memory simulation in SimICS, in Proceedings of the 28th Annual Simulation Symposium (April 1995), pp. 62–73
50.
Zurück zum Zitat P. Mishra, N. Dutt, Processor Description Languages (Morgan Kaufmann Publishers Inc., San Francisco, 2008) P. Mishra, N. Dutt, Processor Description Languages (Morgan Kaufmann Publishers Inc., San Francisco, 2008)
51.
Zurück zum Zitat W.S. Mong, J. Zhu, A retargetable micro-architecture simulator, in Proceedings of the Design Automation Conference, DAC (2003), p. 752 W.S. Mong, J. Zhu, A retargetable micro-architecture simulator, in Proceedings of the Design Automation Conference, DAC (2003), p. 752
52.
Zurück zum Zitat W. Mueller, M. Becker, A. Elfeky, A. DiPasquale, Virtual prototyping of cyber-physical systems, in Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASPDAC (2012), pp. 219–226 W. Mueller, M. Becker, A. Elfeky, A. DiPasquale, Virtual prototyping of cyber-physical systems, in Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASPDAC (2012), pp. 219–226
53.
Zurück zum Zitat A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, A. Hoffmann, A universal technique for fast and flexible instruction-set architecture simulation, in Proceedings of the 39th Design Automation Conference, DAC (2002), pp. 22–27 A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, A. Hoffmann, A universal technique for fast and flexible instruction-set architecture simulation, in Proceedings of the 39th Design Automation Conference, DAC (2002), pp. 22–27
54.
Zurück zum Zitat S. Nussbaum, J.E. Smith, Modeling superscalar processors via statistical simulation, in Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, PACT (2001), pp. 15–24 S. Nussbaum, J.E. Smith, Modeling superscalar processors via statistical simulation, in Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, PACT (2001), pp. 15–24
56.
Zurück zum Zitat A. Pedram, D. Craven, A. Gerstlauer, Modeling cache effects at the transaction level, in Proceedings of the International Embedded Systems Symposium, IESS (2009) A. Pedram, D. Craven, A. Gerstlauer, Modeling cache effects at the transaction level, in Proceedings of the International Embedded Systems Symposium, IESS (2009)
57.
Zurück zum Zitat S. Pees, A. Hoffmann, H. Meyr, Retargetable compiled simulation of embedded processors using a machine description language. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 5(4), 815–834 (2000)CrossRef S. Pees, A. Hoffmann, H. Meyr, Retargetable compiled simulation of embedded processors using a machine description language. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 5(4), 815–834 (2000)CrossRef
58.
Zurück zum Zitat S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr, LISA—machine description language for cycle-accurate models of programmable DSP architectures, in Proceedings of the 36th Annual ACM/IEEE Design Automation Conference, DAC) (1999), pp. 933–938 S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr, LISA—machine description language for cycle-accurate models of programmable DSP architectures, in Proceedings of the 36th Annual ACM/IEEE Design Automation Conference, DAC) (1999), pp. 933–938
59.
Zurück zum Zitat E. Perelman, G. Hamerly, M. Van Biesbrouck, T. Sherwood, B. Calder, Using simpoint for accurate and efficient simulation. SIGMETRICS Perform. Eval. Rev. 31(1), 318–319 (2003)CrossRef E. Perelman, G. Hamerly, M. Van Biesbrouck, T. Sherwood, B. Calder, Using simpoint for accurate and efficient simulation. SIGMETRICS Perform. Eval. Rev. 31(1), 318–319 (2003)CrossRef
60.
Zurück zum Zitat M. Poncino, J. Zhu, DynamoSim: a trace-based dynamically compiled instruction set simulator, in Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, ICCAD (2004), pp. 131–136 M. Poncino, J. Zhu, DynamoSim: a trace-based dynamically compiled instruction set simulator, in Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, ICCAD (2004), pp. 131–136
61.
Zurück zum Zitat H. Posadas, J. Adamez, E. Villar, F. Blasco, F. Escuder, RTOS modeling in systemC for real-time embedded SW simulation: a POSIX model. Des. Autom. Embed. Syst. 10(4), 209–227 (2005)CrossRef H. Posadas, J. Adamez, E. Villar, F. Blasco, F. Escuder, RTOS modeling in systemC for real-time embedded SW simulation: a POSIX model. Des. Autom. Embed. Syst. 10(4), 209–227 (2005)CrossRef
62.
Zurück zum Zitat H. Posadas, L. Díaz, E. Villar, Fast data-cache modeling for native co-simulation, in Proceeding of the Asia and South Pacific Design Automation Conference, ASPDAC (2011) H. Posadas, L. Díaz, E. Villar, Fast data-cache modeling for native co-simulation, in Proceeding of the Asia and South Pacific Design Automation Conference, ASPDAC (2011)
63.
Zurück zum Zitat W. Qin, J. D’Errico, X. Zhu, A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation, in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2006), pp. 193–198 W. Qin, J. D’Errico, X. Zhu, A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation, in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2006), pp. 193–198
64.
Zurück zum Zitat W. Qin, S. Rajagopalan, S. Malik, A formal concurrency model based architecture description language for synthesis of software development tools. SIGPLAN Not. 39(7), 47–56 (2004)CrossRef W. Qin, S. Rajagopalan, S. Malik, A formal concurrency model based architecture description language for synthesis of software development tools. SIGPLAN Not. 39(7), 47–56 (2004)CrossRef
65.
Zurück zum Zitat M. Radetzki, R. Khaligh, Accuracy-adaptive simulation of transaction level models, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2008), pp. 788–791 M. Radetzki, R. Khaligh, Accuracy-adaptive simulation of transaction level models, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2008), pp. 788–791
66.
Zurück zum Zitat R. Rao, M. Oskin, F. Chong, HLSpower: hybrid statistical modeling of the superscalar power-performance design space, in High Performance Computing, vol. 2552, HiPC, ed. by S. Sahni, V. Prasanna, U. Shukla (Springer, Berlin Heidelberg, 2002), pp. 620–629 R. Rao, M. Oskin, F. Chong, HLSpower: hybrid statistical modeling of the superscalar power-performance design space, in High Performance Computing, vol. 2552, HiPC, ed. by S. Sahni, V. Prasanna, U. Shukla (Springer, Berlin Heidelberg, 2002), pp. 620–629
67.
Zurück zum Zitat P. Razaghi, A. Gerstlauer, Automatic timing granularity adjustment for host-compiled software simulation, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2012) P. Razaghi, A. Gerstlauer, Automatic timing granularity adjustment for host-compiled software simulation, in Proceedings of the Asia and South Pacific Design Automation Conference, ASPDAC (2012)
68.
Zurück zum Zitat P. Razaghi, A. Gerstlauer, Multi-core cache hierarchy modeling for host-compiled performance simulation, in Proceedings of the Electronic System Level Synthesis Conference, ESLSyn (2013) P. Razaghi, A. Gerstlauer, Multi-core cache hierarchy modeling for host-compiled performance simulation, in Proceedings of the Electronic System Level Synthesis Conference, ESLSyn (2013)
69.
Zurück zum Zitat P. Razaghi, A. Gerstlauer, Host-compiled multi-core system simulation for early real-time performance evaluation, ACM Trans. Embed. Comput. Syst. (TECS) 13(5s), (2014) P. Razaghi, A. Gerstlauer, Host-compiled multi-core system simulation for early real-time performance evaluation, ACM Trans. Embed. Comput. Syst. (TECS) 13(5s), (2014)
70.
Zurück zum Zitat M. Reshadi, N. Bansal, P. Mishra, N. Dutt, An efficient retargetable framework for instruction-set simulation, in Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2003), pp. 13–18 M. Reshadi, N. Bansal, P. Mishra, N. Dutt, An efficient retargetable framework for instruction-set simulation, in Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS (2003), pp. 13–18
71.
Zurück zum Zitat M. Reshadi, P. Mishra, N. Dutt, Instruction set compiled simulation: a technique for fast and flexible instruction set simulation, in Proceedings of the Design Automation Conference, DAC (2003), pp. 758–763 M. Reshadi, P. Mishra, N. Dutt, Instruction set compiled simulation: a technique for fast and flexible instruction set simulation, in Proceedings of the Design Automation Conference, DAC (2003), pp. 758–763
72.
Zurück zum Zitat M. Rosenblum, S. Herrod, E. Witchel, A. Gupta, Complete computer system simulation: the SimOS approach. IEEE Parallel Distrib. Technol. Syst. Appl. 3(4), 34–43 (1995)CrossRef M. Rosenblum, S. Herrod, E. Witchel, A. Gupta, Complete computer system simulation: the SimOS approach. IEEE Parallel Distrib. Technol. Syst. Appl. 3(4), 34–43 (1995)CrossRef
73.
Zurück zum Zitat G. Schirner, R. Dömer, Result oriented modeling: a novel technique for fast and accurate TLM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) 26(9), 1688–1699 (2007)CrossRef G. Schirner, R. Dömer, Result oriented modeling: a novel technique for fast and accurate TLM. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) 26(9), 1688–1699 (2007)CrossRef
74.
Zurück zum Zitat G. Schirner, R. Dömer, Introducing preemptive scheduling in abstract RTOS models using result oriented modeling, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2008) G. Schirner, R. Dömer, Introducing preemptive scheduling in abstract RTOS models using result oriented modeling, in Proceedings of the Design, Automation and Test in Europe Conference, DATE (2008)
75.
Zurück zum Zitat G. Schirner, A. Gerstlauer, R. Dömer, Fast and accurate processor models for efficient MPSoC design. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 15(2), 101–1026 (2010) G. Schirner, A. Gerstlauer, R. Dömer, Fast and accurate processor models for efficient MPSoC design. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 15(2), 101–1026 (2010)
76.
Zurück zum Zitat K. Scott, N. Kumar, S. Velusamy, B. Childers, J.W. Davidson, M.L. Soffa, Retargetable and reconfigurable software dynamic translation, in Proceedings of the International Symposium on Code Generation and Optimization, CGO (2003) K. Scott, N. Kumar, S. Velusamy, B. Childers, J.W. Davidson, M.L. Soffa, Retargetable and reconfigurable software dynamic translation, in Proceedings of the International Symposium on Code Generation and Optimization, CGO (2003)
77.
Zurück zum Zitat H. Shi, Y. Wang, H. Guan, A. Liang, An intermediate language level optimization framework for dynamic binary translation. SIGPLAN Not. 42(5), 3–9 (2007)CrossRef H. Shi, Y. Wang, H. Guan, A. Liang, An intermediate language level optimization framework for dynamic binary translation. SIGPLAN Not. 42(5), 3–9 (2007)CrossRef
78.
Zurück zum Zitat S. Stattelmann, O. Bringmann, W. Rosenstiel, Fast and accurate resource conflict simulation for performance analysis of multi-core systems, in Design, Automation Test in Europe Conference Exhibition, DATE (2011) S. Stattelmann, O. Bringmann, W. Rosenstiel, Fast and accurate resource conflict simulation for performance analysis of multi-core systems, in Design, Automation Test in Europe Conference Exhibition, DATE (2011)
79.
Zurück zum Zitat S. Stattelmann, O. Bringmann, W. Rosenstiel, Fast and accurate source-level simulation of software timing considering complex code optimizations, in Proceedings of the 48th Design Automation Conference, DAC (2011), pp 486–491 S. Stattelmann, O. Bringmann, W. Rosenstiel, Fast and accurate source-level simulation of software timing considering complex code optimizations, in Proceedings of the 48th Design Automation Conference, DAC (2011), pp 486–491
80.
Zurück zum Zitat S. Sutarwala, P.G. Paulin, Y. Kumar, Insulin: an instruction set simulation environment, in Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, CHDL (1993), pp. 369–376 S. Sutarwala, P.G. Paulin, Y. Kumar, Insulin: an instruction set simulation environment, in Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, CHDL (1993), pp. 369–376
81.
Zurück zum Zitat X. Vera, J. Xue, Let’s study whole-program cache behaviour analytically, in Proceedings of the 8th International Symposium on High-Performance Computer Architecture, HPCA (2002), p. 175 X. Vera, J. Xue, Let’s study whole-program cache behaviour analytically, in Proceedings of the 8th International Symposium on High-Performance Computer Architecture, HPCA (2002), p. 175
82.
Zurück zum Zitat Z. Wang, J. Henkel, Accurate source-level simulation of embedded software with respect to compiler optimizations, in Proceedings of the Design, Automation Test in Europe Conference, DATE (2012) Z. Wang, J. Henkel, Accurate source-level simulation of embedded software with respect to compiler optimizations, in Proceedings of the Design, Automation Test in Europe Conference, DATE (2012)
83.
Zurück zum Zitat E. Witchel, M. Rosenblum, Embra: fast and flexible machine simulation, in Proceedings of the 1996 ACM International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS (1996), pp. 68–79 E. Witchel, M. Rosenblum, Embra: fast and flexible machine simulation, in Proceedings of the 1996 ACM International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS (1996), pp. 68–79
84.
Zurück zum Zitat R. Wunderlich, T. Wenisch, B. Falsafi, J. Hoe, SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling, in Proceedings of the 30th Annual International Symposium on Computer Architecture, ISCA (2003), pp. 84–95 R. Wunderlich, T. Wenisch, B. Falsafi, J. Hoe, SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling, in Proceedings of the 30th Annual International Symposium on Computer Architecture, ISCA (2003), pp. 84–95
85.
Zurück zum Zitat H. Zabel, W. Müller, A. Gerstlauer, Accurate RTOS modeling and analysis with SystemC, in Hardware-dependent Software: Principles and Practice, ed. by W. Ecker, W. Müller, R. Dömer (Springer, Dordrecht, 2009) H. Zabel, W. Müller, A. Gerstlauer, Accurate RTOS modeling and analysis with SystemC, in Hardware-dependent Software: Principles and Practice, ed. by W. Ecker, W. Müller, R. Dömer (Springer, Dordrecht, 2009)
86.
Zurück zum Zitat Z. Zhao, A. Gerstlauer, L.K. John, Source-level performance, energy, reliability, power and thermal (PERPT) simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) (2016) Z. Zhao, A. Gerstlauer, L.K. John, Source-level performance, energy, reliability, power and thermal (PERPT) simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) (2016)
87.
Zurück zum Zitat J. Zhu, D.D. Gajski, An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. 10(3), 363–373 (2002)CrossRef J. Zhu, D.D. Gajski, An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. 10(3), 363–373 (2002)CrossRef
88.
Zurück zum Zitat G. Zimmermann, The MIMOLA design system a computer aided digital processor design method, in Proceedings of the 16th Design Automation Conference, DAC (1979), pp. 53–58 G. Zimmermann, The MIMOLA design system a computer aided digital processor design method, in Proceedings of the 16th Design Automation Conference, DAC (1979), pp. 53–58
89.
Zurück zum Zitat V. Zivojnović, S. Tjiang, H. Meyr, Compiled simulation of programmable DSP architectures. J. VLSI Signal Process. Syst. 16(1), 73–80 (1997)CrossRef V. Zivojnović, S. Tjiang, H. Meyr, Compiled simulation of programmable DSP architectures. J. VLSI Signal Process. Syst. 16(1), 73–80 (1997)CrossRef
Metadaten
Titel
Virtual Prototyping of Embedded Systems: Speed and Accuracy Tradeoffs
verfasst von
Vania Joloboff
Andreas Gerstlauer
Copyright-Jahr
2017
Verlag
Springer Singapore
DOI
https://doi.org/10.1007/978-981-10-4436-6_1

Premium Partner