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Erschienen in:
1987 | OriginalPaper | Buchkapitel
VLSI Circuit Analysis, Timing Verification and Optimization
verfasst von : Albert E. Ruehli, Daniel L. Ostapko
Erschienen in: VLSI CAD Tools and Applications
Verlag: Springer US
Enthalten in: Professional Book Archive
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In this paper, we give an overview of the state-of-the-art in Circuit Analysis, Timing Verification, and Optimization. Emphasis is given to circuit analysis, timing verification and optimization since simulation is covered by C. Terman in this book. Also, the optimization of large circuits is receiving new attention due to the need for timing performance improvement in silicon compilation.