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Erschienen in:
2008 | OriginalPaper | Buchkapitel
VLSI Implementation of Discrete Wavelet Transform using Systolic Array Architecture
verfasst von : S.Sankar Sumanth, K.A.Narayanan Kutty
Erschienen in: Advances in Computer and Information Sciences and Engineering
Verlag: Springer Netherlands
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In this paper, we introduce an architectural design for efficient hardware acceleration of the Discrete Wavelet Transform. The unit designed can be used to accelerate multimedia applications as JPEG2000. The design is based on the Systolic Architecture Design for Discrete Wavelet Transform, which is a fast implementation of the Discrete Wavelet Transform. The design utilizes various techniques such as pipelining, data reusability, parallel execution and specific features of the Xilinx (Core Generator) Spartan II to accelerate the transform. For performance analysis, simulators like (Model-Sim 5.8c, MATLAB 7.1) were used along with xilinx ISE. The Matlab simulator was used to see the images obtained at intermediate stages and check the performance at each stage.