A CAD approach for suppression of power supply noise and performance analysis of some multi-core processors in pre-layout stage

In modern system-on-chip, the number of transistors has grown exponentially. This requires an efficient electrical power distribution network for proper functioning of the chip. Voltages at different nodes with respect to the desired level may vary which correspond to generation of supply noise. This paper deals with the estimation and allocation of decoupling capacitance for reduction of supply noise at the pre-layout level. Usually, decoupling capacitors are placed near the noisy functional modules, which acts as local charge storing devices and effectively reduce the transients. In this work, analysis of various sources of supply noises has been performed. Depending on the amount of supply noise, the decoupling capacitance has been estimated and allocated with minimum increment in power consumption and propagation delay. We have considered 512-points, 1-k point, 2-k point and 4-k point Fast Fourier Transform processors and International Test Conference 1999 (b14 and b17) benchmark circuits as our test circuits. This work reports up to 51.9% reduction of peak supply noise at the cost of 0.48 and 1.44% increase in power consumption and delay respectively. This estimation and subsequent allocation of decoupling capacitances will help for more accurate design and implementation at the layout stage.