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Erschienen in:
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2018 | OriginalPaper | Buchkapitel

2. ADC Architecture

verfasst von : Weitao Li, Fule Li, Zhihua Wang

Erschienen in: High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications

Verlag: Springer International Publishing

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Abstract

A successful low-power architecture is extremely important for the high-performance ADC. It helps to save the power dissipation in the systematic level. We focus on the architecture design of the low-power and high-performance ADC in this chapter. First, the traditional architectures, including the flash ADC, the SAR ADC, and the pipelined ADC, are briefly depicted and the limitations are discussed. To try to exceed the limitations, the improvement of the pipelined ADC and the SAR ADC are presented in the following sections. Then to reduce the power dissipation further, two hybrid architectures are discussed. After that, we talk about the time-interleaved ADC. At the end, we sum up the architectures for the low-power and high-performance ADC.

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Vorheriges Kapitel Introduction
Nächstes Kapitel Reference Voltage Buffer
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Metadaten
Titel
ADC Architecture
verfasst von
Weitao Li
Fule Li
Zhihua Wang
Copyright-Jahr
2018
Buch
High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications

Print ISBN: 978-3-319-62011-4

Electronic ISBN: 978-3-319-62012-1

Copyright-Jahr: 2018

DOI
https://doi.org/10.1007/978-3-319-62012-1_2

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