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2018 | OriginalPaper | Buchkapitel

3. Reference Voltage Buffer

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Abstract

Reference voltage is a ruler that is used by the ADC to weight the analog input. Accurate reference voltage plays an important role in the high-speed and high-resolution data conversion. In this chapter, we focus on the reference voltage buffer design. First, the traditional narrow-bandwidth buffer and wide-bandwidth buffer are depicted. The narrow-bandwidth one usually needs the large decoupling capacitors, which are difficult to be integrated on chip. The wide-bandwidth one normally consumes the large static current. Second, two reference buffers are introduced to exceed the limitations of the traditional designs. They are the level-shifter-aided reference buffer and the charge-compensation-based reference buffer. As a wide-bandwidth buffer, the level-shifter-aided reference buffer effectively saves the power dissipation. As a narrow-bandwidth buffer, the charge-compensation-based buffer does not need the large decoupling capacitors. At the end, we sum up the buffer designs for the low-power and high-performance ADC.

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Literatur
1.
Zurück zum Zitat B.G. Lee, B.M. Min, G. Manganaro, J.W. Valvano, A 14-b 100-ms/s pipelined adc with a merged sha and first mdac. IEEE J. Solid-State Circuits 43, 2613–2619 (2008). DecCrossRef B.G. Lee, B.M. Min, G. Manganaro, J.W. Valvano, A 14-b 100-ms/s pipelined adc with a merged sha and first mdac. IEEE J. Solid-State Circuits 43, 2613–2619 (2008). DecCrossRef
2.
Zurück zum Zitat Y.J. Cho, K.H. Lee, H.C. Choi, S.H. Lee, K.H. Moon, J.W. Kim, A calibration-free 14b 70ms/s 3.3mm2 235mw 0.13um cmos pipeline adc with high-matching 3-d symmetric capacitors, in IEEE Custom Integrated Circuits Conference 2006, pp. 485–488, Sept 2006 Y.J. Cho, K.H. Lee, H.C. Choi, S.H. Lee, K.H. Moon, J.W. Kim, A calibration-free 14b 70ms/s 3.3mm2 235mw 0.13um cmos pipeline adc with high-matching 3-d symmetric capacitors, in IEEE Custom Integrated Circuits Conference 2006, pp. 485–488, Sept 2006
3.
Zurück zum Zitat K. Gulati, M. Peng, A. Pulincherry, C. Munoz, M. Lugin, A. Bugeja, J. Li, A. Chandrakasan, A highly-integrated cmos analog baseband transceiver with 180msps 13b pipelined cmos adc and dual 12b dacs, in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, pp. 515–518, Sept 2005 K. Gulati, M. Peng, A. Pulincherry, C. Munoz, M. Lugin, A. Bugeja, J. Li, A. Chandrakasan, A highly-integrated cmos analog baseband transceiver with 180msps 13b pipelined cmos adc and dual 12b dacs, in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, pp. 515–518, Sept 2005
4.
Zurück zum Zitat T. Nezuka, K. Misawa, J. Azami, Y. Majima, J.I. Okamura, A 10-bit 200ms/s pipeline a/d converter for high-speed video signal digitizer, in Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, pp. 31–34, Nov 2006 T. Nezuka, K. Misawa, J. Azami, Y. Majima, J.I. Okamura, A 10-bit 200ms/s pipeline a/d converter for high-speed video signal digitizer, in Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, pp. 31–34, Nov 2006
5.
Zurück zum Zitat Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, K.-D. Kim, W.-Y. Lee, K.-T. Hong, J.-K. Kwon, A 9.15mw 0.22mm2 10b 204ms/s pipelined sar adc in 65nm cmos, in Custom Integrated Circuits Conference (CICC), 2010 IEEE, pp. 1–4, Sept 2010 Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, K.-D. Kim, W.-Y. Lee, K.-T. Hong, J.-K. Kwon, A 9.15mw 0.22mm2 10b 204ms/s pipelined sar adc in 65nm cmos, in Custom Integrated Circuits Conference (CICC), 2010 IEEE, pp. 1–4, Sept 2010
6.
Zurück zum Zitat S. Khalid, Voltage buffer for capacitive loads. Patent US 7002401 B2, 2006 S. Khalid, Voltage buffer for capacitive loads. Patent US 7002401 B2, 2006
7.
Zurück zum Zitat Y.-M. Liao, Y.-H. Lin, Reference buffer circuits for providing reference voltages. Patent US 7956597 B2, 2011 Y.-M. Liao, Y.-H. Lin, Reference buffer circuits for providing reference voltages. Patent US 7956597 B2, 2011
8.
Zurück zum Zitat C. Yang, F. Li, W. Li, X. Wang, Z. Wang, An 85 mw 14-bit 150 ms/s pipelined adc with 71.3 db peak sndr in 130 nm cmos, in Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian, pp. 85–88, Nov 2013 C. Yang, F. Li, W. Li, X. Wang, Z. Wang, An 85 mw 14-bit 150 ms/s pipelined adc with 71.3 db peak sndr in 130 nm cmos, in Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian, pp. 85–88, Nov 2013
9.
Zurück zum Zitat Y. Miyahara, M. Sano, K. Koyama, T. Suzuki, K. Hamashita, B.S. Song, Adaptive cancellation of gain and nonlinearity errors in pipelined adcs, in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 282–283, Feb 2013 Y. Miyahara, M. Sano, K. Koyama, T. Suzuki, K. Hamashita, B.S. Song, Adaptive cancellation of gain and nonlinearity errors in pipelined adcs, in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 282–283, Feb 2013
10.
Zurück zum Zitat D.H. Hwang, J.E. Song, S.P. Nam, H.J. Kim, T.J. An, K.S. Kim, S.H. Lee, A range-scaled 13b 100ms/s 0.13 \(\mu \)m cmos sha-free adc based on a single reference, in SoC Design Conference (ISOCC), 2011 International, pp. 62–65, Nov 2011 D.H. Hwang, J.E. Song, S.P. Nam, H.J. Kim, T.J. An, K.S. Kim, S.H. Lee, A range-scaled 13b 100ms/s 0.13 \(\mu \)m cmos sha-free adc based on a single reference, in SoC Design Conference (ISOCC), 2011 International, pp. 62–65, Nov 2011
11.
Zurück zum Zitat C.H. Lee, C.H. Hou, C.P. Huang, S.J. Chang, Y.T. Hsieh, Y.Z. Juang, A 2.5-bit/cycle 10-bit 160-ms/s sar adc in 90-nm cmos process, in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2016, pp. 1–4 C.H. Lee, C.H. Hou, C.P. Huang, S.J. Chang, Y.T. Hsieh, Y.Z. Juang, A 2.5-bit/cycle 10-bit 160-ms/s sar adc in 90-nm cmos process, in 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2016, pp. 1–4
12.
Zurück zum Zitat Y.Z. Lin, C.C. Liu, G.Y. Huang, Y.T. Shyu, S.J. Chang, A 9-bit 150-ms/s 1.53-mw subranged sar adc in 90-nm cmos, in 2010 Symposium on VLSI Circuits, pp. 243–244, June 2010 Y.Z. Lin, C.C. Liu, G.Y. Huang, Y.T. Shyu, S.J. Chang, A 9-bit 150-ms/s 1.53-mw subranged sar adc in 90-nm cmos, in 2010 Symposium on VLSI Circuits, pp. 243–244, June 2010
13.
Zurück zum Zitat H. Wei, C.H. Chan, U.F. Chio, S.W. Sin, U. Seng-Pan, R. Martins, F. Maloberti, A 0.024 mm2 8b 400 ms/s sar adc with 2b/cycle and resistive dac in 65 nm cmos, in 2011 IEEE International Solid-State Circuits Conference, Feb 2011, pp. 188–190 H. Wei, C.H. Chan, U.F. Chio, S.W. Sin, U. Seng-Pan, R. Martins, F. Maloberti, A 0.024 mm2 8b 400 ms/s sar adc with 2b/cycle and resistive dac in 65 nm cmos, in 2011 IEEE International Solid-State Circuits Conference, Feb 2011, pp. 188–190
Metadaten
Titel
Reference Voltage Buffer
verfasst von
Weitao Li
Fule Li
Zhihua Wang
Copyright-Jahr
2018
DOI
https://doi.org/10.1007/978-3-319-62012-1_3

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