An efficient design and implementation of Vedic multiplier in quantum-dot cellular automata

The Quantum-Dot Cellular Automata (QCA) is an incipient nanotechnology in contrast to the CMOS technology with appealing features like low power consumption, high speed and reduced size in implementing the architecture for the computations. QCA provides better and well-organised solution with a modern and exclusive result in performing logical computations at Nano-scale. In this paper mainly focused on design and implementation of 8 \(\times \) 8 Vedic multiplier with the help of 4 \(\times \) 4 Vedic multiplier using Nikhilam and Anurupayan Sutra. The simulation results achieved with the help of QCA Designer tool shows that the area and delay of the proposed 8 \(\times \) 8 Vedic multiplier is decreased by an average of 45.8% and 72.6%, 82.5% and 80.7%, and 17.24% and 21% respectively when compared to 8 \(\times \) 8 Array multiplier, 8 \(\times \) 8 Wallace multiplier, and 8 \(\times \) 8 Urdhva Tiryagbhyam Vedic multiplier. Furthermore, the proposed multiplier is implemented on Kintex-7 (KC705) FPGA board. The results revealed a reduction in area and delay compared to a well-known prior art multipliers.