Skip to main content
Erschienen in: Journal of Cryptographic Engineering 4/2018

09.05.2017 | Regular Paper

Another dimension in integrated circuit trust

verfasst von: John DeVale, Ryan Rakvic, Kevin Rudd

Erschienen in: Journal of Cryptographic Engineering | Ausgabe 4/2018

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Although 3D integrated circuit technology has typically been used to solve specific design goals, it has great potential for protecting intellectual property from theft or unwanted modification while at a third-party fabrication facility. We present analysis of a technique for splitting a design across multiple die layers for this purpose. From the perspective of a third-party, this technique effectively encrypts the circuit, preventing unauthorized use of, or alteration to, the design. The device is “unencrypted” at a secure final assembly location where it is oriented and bonded according to its secret key. As is true for any cryptographic technique, analysis of the algorithm or implementation may result in attacks with lower combinatorial complexity. We look at some of these potential attacks and discuss a number of possible solutions. Finally, we introduce the inter-die routing layer, which effectively complements the 3D splitting technique, making it much more difficult to develop attacks to bypass a brute force approach.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Bernstein, K.: Introduction to 3D integration. In: International Solid State Circuits Conference Tutorial, (2006) Bernstein, K.: Introduction to 3D integration. In: International Solid State Circuits Conference Tutorial, (2006)
2.
Zurück zum Zitat Das, S., Fan, A., Chen, K.-N., Tan, C.S., Checka, N., Reif, R.: Technology, performance, and computer-aided design of three-dimensional integrated circuits. In: Proceedings of International Symposim on Physical Design (ISPD’97), New York, ACM Press, pp. 108–115 (2004) Das, S., Fan, A., Chen, K.-N., Tan, C.S., Checka, N., Reif, R.: Technology, performance, and computer-aided design of three-dimensional integrated circuits. In: Proceedings of International Symposim on Physical Design (ISPD’97), New York, ACM Press, pp. 108–115 (2004)
3.
Zurück zum Zitat Davis, W.R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A.M., Steer, M., Franzon, P.D.: Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des. Test Comput. 22, 498–510 (2005)CrossRef Davis, W.R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A.M., Steer, M., Franzon, P.D.: Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des. Test Comput. 22, 498–510 (2005)CrossRef
4.
Zurück zum Zitat Deng, Y., Maly, W.: 2.5D system integration: a design driven system implementation schema. In: Proceedings of the Conference on Asia South Pacific Design Automation, (2004) Deng, Y., Maly, W.: 2.5D system integration: a design driven system implementation schema. In: Proceedings of the Conference on Asia South Pacific Design Automation, (2004)
5.
Zurück zum Zitat Reif, R., Fan, A., Chen, K., Das, S.: Fabrication technologies for three-dimensional integrated circuits. In: Proceedings of the International Symposium on Quality Electronic Devices, pp. 33–37 (2002) Reif, R., Fan, A., Chen, K., Das, S.: Fabrication technologies for three-dimensional integrated circuits. In: Proceedings of the International Symposium on Quality Electronic Devices, pp. 33–37 (2002)
6.
Zurück zum Zitat Xue, L., Liu, C., Tiwari, S.: Multi-layers with buried structures (MLBS): an approach to three-dimensional integration. In: Proceedings of the IEEE International Conference on Silicon On Insulator, pp. 117–118 (2001) Xue, L., Liu, C., Tiwari, S.: Multi-layers with buried structures (MLBS): an approach to three-dimensional integration. In: Proceedings of the IEEE International Conference on Silicon On Insulator, pp. 117–118 (2001)
7.
Zurück zum Zitat Knickerbocker, J.U., et al.: Three-dimensional silicon integration. IBM J. Res. Tech. IBM J. Res. Dev. 52(6), 553–569 (2008)CrossRef Knickerbocker, J.U., et al.: Three-dimensional silicon integration. IBM J. Res. Tech. IBM J. Res. Dev. 52(6), 553–569 (2008)CrossRef
8.
Zurück zum Zitat Pavlidis, V., Friedman, E.: Three-Dimensional Integrated Circuit Design. Morgan Kaufmann, Burlington (2009) Pavlidis, V., Friedman, E.: Three-Dimensional Integrated Circuit Design. Morgan Kaufmann, Burlington (2009)
9.
Zurück zum Zitat Jiang, T., Luo, S.: 3D integration—present and future. In: Proceedings of the 10th Electronics Packaging Technology Conference, pp. 373–378 (2008) Jiang, T., Luo, S.: 3D integration—present and future. In: Proceedings of the 10th Electronics Packaging Technology Conference, pp. 373–378 (2008)
10.
Zurück zum Zitat Black, B., Nelson, D.W., Webb, C., Samra, N.: 3D processing technology and its impact on iA32 microprocessors. In: IEEE International Conference on Computer Design, pp. 316–318 (2004) Black, B., Nelson, D.W., Webb, C., Samra, N.: 3D processing technology and its impact on iA32 microprocessors. In: IEEE International Conference on Computer Design, pp. 316–318 (2004)
11.
Zurück zum Zitat Miura, N. Mizoguchi, D., Inoue, M., Tsuji, H., Sakurai, T., Kuroda, T.: A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme. In: ISSCC Digest of Technical Papers, pp. 264–265 (2005) Miura, N. Mizoguchi, D., Inoue, M., Tsuji, H., Sakurai, T., Kuroda, T.: A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme. In: ISSCC Digest of Technical Papers, pp. 264–265 (2005)
12.
Zurück zum Zitat Johnson, V.N., Jozwiak, J., Moll, A.: Through wafer interconnects on active pMOS devices. In: IEEE Workshop on Microelectronics and Electron Devices, pp. 82–84 (2004) Johnson, V.N., Jozwiak, J., Moll, A.: Through wafer interconnects on active pMOS devices. In: IEEE Workshop on Microelectronics and Electron Devices, pp. 82–84 (2004)
13.
Zurück zum Zitat Rousseau1, M., Rozeau, O., Cibrario, G., Le Carval, G., Jaud, M.-A., Leduc, P., Farcy, A., Marty, A.: Through-silicon via based 3D IC technology: electrostatic simulations for design methodology. In: IMAPS Device Packaging Conference, Phoenix, AZ (2008) Rousseau1, M., Rozeau, O., Cibrario, G., Le Carval, G., Jaud, M.-A., Leduc, P., Farcy, A., Marty, A.: Through-silicon via based 3D IC technology: electrostatic simulations for design methodology. In: IMAPS Device Packaging Conference, Phoenix, AZ (2008)
14.
Zurück zum Zitat Andry, P.S., et al.: Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. IBM J. Res. Technol. IBM J. Res. Dev 52(6), 571–581 (2008)CrossRef Andry, P.S., et al.: Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. IBM J. Res. Technol. IBM J. Res. Dev 52(6), 571–581 (2008)CrossRef
15.
Zurück zum Zitat Jung, S.M., Jang, J., Cho, W., Moon, J., Kwak, K., Choi, B., Hwang, B., Lim, H., Jeong, J. Kim, J., Kim, K.: The revolutionary and truly 3-dimentional 25F2 SRAM technology with the smallest S3 cell, 0.16\(\upmu \)m2 and SSTFF for ultra high density SRAM. In: VLSI Technical Digest of Technical Papers, pp. 228–229 (2004) Jung, S.M., Jang, J., Cho, W., Moon, J., Kwak, K., Choi, B., Hwang, B., Lim, H., Jeong, J. Kim, J., Kim, K.: The revolutionary and truly 3-dimentional 25F2 SRAM technology with the smallest S3 cell, 0.16\(\upmu \)m2 and SSTFF for ultra high density SRAM. In: VLSI Technical Digest of Technical Papers, pp. 228–229 (2004)
16.
Zurück zum Zitat Mayega, J., Erdogan, O., Belemjian, P.M., Zhou, K., Mcdonald, J.F., Kraft, R.P.: 3D direct vertical interconnect microprocessors test vehicle. In: Proceedings of the ACM Great Lakes Sympopsium on VLSI, Washington, DC, pp. 141–146 (2003) Mayega, J., Erdogan, O., Belemjian, P.M., Zhou, K., Mcdonald, J.F., Kraft, R.P.: 3D direct vertical interconnect microprocessors test vehicle. In: Proceedings of the ACM Great Lakes Sympopsium on VLSI, Washington, DC, pp. 141–146 (2003)
17.
Zurück zum Zitat Puttaswamy, K., Loh, G.H.: Implementing caches in a 3D technology for high performance processors. In: Proceedings of the International Conference on Computer Design, San Jose, CA (2005) Puttaswamy, K., Loh, G.H.: Implementing caches in a 3D technology for high performance processors. In: Proceedings of the International Conference on Computer Design, San Jose, CA (2005)
18.
Zurück zum Zitat Rahman, A., Reif, R.: System level performance evaluation of three-dimensional integrated circuits. IEEE Trans. VLSI Syst. 8(6), 671–678 (2000)CrossRef Rahman, A., Reif, R.: System level performance evaluation of three-dimensional integrated circuits. IEEE Trans. VLSI Syst. 8(6), 671–678 (2000)CrossRef
19.
Zurück zum Zitat Tsai, Y., Xie, Y., Narayanan, V., Irwin, M.J.: Three-dimensional cache design exploration using 3dcacti. In: Proceedings of the IEEE International Conference on Computer Design (ICCD’05), pp. 519–524 (2005) Tsai, Y., Xie, Y., Narayanan, V., Irwin, M.J.: Three-dimensional cache design exploration using 3dcacti. In: Proceedings of the IEEE International Conference on Computer Design (ICCD’05), pp. 519–524 (2005)
20.
Zurück zum Zitat Dong, X., Xie, Y.: System-level cost analysis and design exploration for 3D ICs. In: Asia and South Pacific Design Automation Conference (2009) Dong, X., Xie, Y.: System-level cost analysis and design exploration for 3D ICs. In: Asia and South Pacific Design Automation Conference (2009)
21.
Zurück zum Zitat Pope, S.: Trusted integrated circuit strategy. IEEE Trans. Compon. Packag. Technol. 31(1), 230–234 (2008)CrossRef Pope, S.: Trusted integrated circuit strategy. IEEE Trans. Compon. Packag. Technol. 31(1), 230–234 (2008)CrossRef
22.
Zurück zum Zitat Wu, Z., Weaver, A.: Hybrid trust information exchange for federated systems. In: IEEE International Symposium on Dependable, Autonomic and Secure Computing, pp. 125–133 (2007) Wu, Z., Weaver, A.: Hybrid trust information exchange for federated systems. In: IEEE International Symposium on Dependable, Autonomic and Secure Computing, pp. 125–133 (2007)
23.
Zurück zum Zitat Xu, G., Borcea, C., Iftode, L.: A policy enforcing mechanism for trusted Ad hoc networks. IEEE Trans. Dependable Secure Comput. 8(3), 321–336 (2011) Xu, G., Borcea, C., Iftode, L.: A policy enforcing mechanism for trusted Ad hoc networks. IEEE Trans. Dependable Secure Comput. 8(3), 321–336 (2011)
24.
Zurück zum Zitat Imeson, F., Emtenan, A., Garg, S., Tripunitara, M.V.: Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation. In: USENIX Security (Vol. 13) (2013) Imeson, F., Emtenan, A., Garg, S., Tripunitara, M.V.: Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation. In: USENIX Security (Vol. 13) (2013)
25.
Zurück zum Zitat Adee, S.: The hunt for the kill switch. IEEE Spectrum 45(5), 34–39 (2008)CrossRef Adee, S.: The hunt for the kill switch. IEEE Spectrum 45(5), 34–39 (2008)CrossRef
26.
Zurück zum Zitat King, S.T., Tucek, J., Cozzie, A., Grier, C., Jiang, W., Zhou, Y.: Designing and Implementing Malicious Hardware. LEET 8, 1–8 (2008) King, S.T., Tucek, J., Cozzie, A., Grier, C., Jiang, W., Zhou, Y.: Designing and Implementing Malicious Hardware. LEET 8, 1–8 (2008)
27.
Zurück zum Zitat Skorobogatov, S., Woods, C.: Breakthrough silicon scanning discovers backdoor in military chip. In: International Workshop on Cryptographic Hardware and Embedded Systems (pp. 23-40). Springer, Berlin, Heidelberg (2012)CrossRef Skorobogatov, S., Woods, C.: Breakthrough silicon scanning discovers backdoor in military chip. In: International Workshop on Cryptographic Hardware and Embedded Systems (pp. 23-40). Springer, Berlin, Heidelberg (2012)CrossRef
28.
Zurück zum Zitat Bhunia, S., Hsiao, M.S., Banga, M., Narasimhan, S.: Hardware Trojan attacks: threat analysis and countermeasures. Proc. IEEE 102(8), 1229–1247 (2014)CrossRef Bhunia, S., Hsiao, M.S., Banga, M., Narasimhan, S.: Hardware Trojan attacks: threat analysis and countermeasures. Proc. IEEE 102(8), 1229–1247 (2014)CrossRef
30.
Zurück zum Zitat Tehranipoor, M., Koushanfar, F.: A survey of hardware trojan taxonomy and detection. IEEE Des. Test Com. 27(1), 10–25 (2010) Tehranipoor, M., Koushanfar, F.: A survey of hardware trojan taxonomy and detection. IEEE Des. Test Com. 27(1), 10–25 (2010)
31.
Zurück zum Zitat Dziembowski, S., Faust, S., Standaert, F. X.: Private circuits III: Hardware Trojan-Resilience via testing amplification. In: Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security (pp. 142-153). ACM (2016) Dziembowski, S., Faust, S., Standaert, F. X.: Private circuits III: Hardware Trojan-Resilience via testing amplification. In: Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security (pp. 142-153). ACM (2016)
33.
Zurück zum Zitat Gu, P., Li, S., Stow, D., Barnes, R., Liu, L., Xie, Y., Kursun, E.: Leveraging 3D technologies for hardware security: opportunities and challenges. In: Proceedings of the 26th edition on Great Lakes Symposium on VLSI (pp. 347-352). ACM (2016) Gu, P., Li, S., Stow, D., Barnes, R., Liu, L., Xie, Y., Kursun, E.: Leveraging 3D technologies for hardware security: opportunities and challenges. In: Proceedings of the 26th edition on Great Lakes Symposium on VLSI (pp. 347-352). ACM (2016)
34.
Zurück zum Zitat Vaidyanathan, K., Liu, R., Sumbul, E., Zhu, Q., Franchetti, F., Pileggi, L.: Efficient and secure intellectual property (IP) design with split fabrication. In: Hardware-Oriented Security and Trust (HOST), 2014 IEEE International Symposium on IEEE, pp. 13-18 (2014) Vaidyanathan, K., Liu, R., Sumbul, E., Zhu, Q., Franchetti, F., Pileggi, L.: Efficient and secure intellectual property (IP) design with split fabrication. In: Hardware-Oriented Security and Trust (HOST), 2014 IEEE International Symposium on IEEE, pp. 13-18 (2014)
35.
Zurück zum Zitat Jagasivamani, M., Gadfort, P., Sika, M., Bajura, M., Fritze, M.: Split-fabrication obfuscation: metrics and techniques. In: Hardware-Oriented Security and Trust (HOST), 2014 IEEE International Symposium on, IEEE pp. 7–12 (2014) Jagasivamani, M., Gadfort, P., Sika, M., Bajura, M., Fritze, M.: Split-fabrication obfuscation: metrics and techniques. In: Hardware-Oriented Security and Trust (HOST), 2014 IEEE International Symposium on, IEEE pp. 7–12 (2014)
36.
Zurück zum Zitat Xiao, K., Forte, D., Jin, Y., Karri, R., Bhunia, S., Tehranipoor, M.: Hardware Trojans: lessons learned after one decade of research. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 22(1), 6 (2016) Xiao, K., Forte, D., Jin, Y., Karri, R., Bhunia, S., Tehranipoor, M.: Hardware Trojans: lessons learned after one decade of research. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 22(1), 6 (2016)
Metadaten
Titel
Another dimension in integrated circuit trust
verfasst von
John DeVale
Ryan Rakvic
Kevin Rudd
Publikationsdatum
09.05.2017
Verlag
Springer Berlin Heidelberg
Erschienen in
Journal of Cryptographic Engineering / Ausgabe 4/2018
Print ISSN: 2190-8508
Elektronische ISSN: 2190-8516
DOI
https://doi.org/10.1007/s13389-017-0164-7

Weitere Artikel der Ausgabe 4/2018

Journal of Cryptographic Engineering 4/2018 Zur Ausgabe

Premium Partner