Automated design space exploration for FPGA-based heterogeneous interconnects

The choice of the on-chip communication topology in many systems is of vital importance because it affects the entire inter-component data traffic and impacts significantly the overall system performance and cost. On the other hand, there is today a very large spectrum of on-chip interconnect topologies that potentially meet given communication requirements, determining various trade-offs between cost and performance. This work proposes an automated methodology to search the interconnect design space, avoiding a manual and time consuming try-and-error process. The methodology turns the description of the application communication requirements into an on-chip synthesizable interconnection structure satisfying given area constraints. Targeted at FPGA technologies, the approach combines crossbars and shared buses, connected through bridges, yielding a scalable, efficient structure. The resulting architecture improves the level of communication parallelism that can be exploited, while keeping area requirements low. The paper thoroughly describes the formalisms and the methodology used to derive such optimized heterogeneous topologies. It also discusses some case-studies emphasizing the impact of the proposed approach and highlighting the essential differences with a few other solutions presented in the technical literature.