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2011 | OriginalPaper | Buchkapitel

4. Combination of Redundancy and Error Correction

verfasst von : Dr. Masashi Horiguchi, Dr. Kiyoo Itoh

Erschienen in: Nanoscale Memory Repair

Verlag: Springer New York

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Abstract

The effects of redundancy and error checking and correction (ECC) are separately discussed in the previous chapters. However, more faults can be repaired by the combination of the redundancy and the ECC than by simply adding the effects of them. This synergistic effect, which was first reported in 1990 [1], is especially effective for repairing random-bit faults. Repairing many random-bit faults by redundancy is not effective. Since the replacement unit is usually a row or a column, bit faults require as many spare rows/columns except for the case of two or more bit faults located on the same row/column. On the contrary, ECC can potentially repair many random-bit faults. However, ECC using a single-error correction code can practically repair far fewer bit faults because the probability of “fault collision” (two or more faults being located in a code word) cannot be neglected as described in Sect. 3.6. By combining the redundancy and ECC, most bit faults are repaired by ECC and a few “fault collisions” are repaired by redundancy, resulting in dramatic increase of repairable faults [1–3].

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Metadaten
Titel
Combination of Redundancy and Error Correction
verfasst von
Dr. Masashi Horiguchi
Dr. Kiyoo Itoh
Copyright-Jahr
2011
Verlag
Springer New York
DOI
https://doi.org/10.1007/978-1-4419-7958-2_4

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