Compact and High Speed Architectures of KASUMI Block Cipher

This paper proposes highly compact and high speed hardware architectures of 64-bit KASUMI block cipher for wide range of wireless applications. A novel methodology is adopted for low area KASUMI implementation employing a single combined substitution block (CSB) for S9 and S7 substitution functions in FI/FO function. The CSB performs S9/S7 transformations and re-utilizes the common combinational logic of AND and AND–XOR gates whereas computations of CSB logic expressions are performed using parallel hierarchy of ANDs/AND-XORs. This scheme substantially reduces the area generating moderate throughput values for compact KASUMI architecture. FPGA implementation with Xilinx Virtex 7 and ASIC implementation using IC Design Compiler, 0.18 µm at 1.8 V constituted 126 CLB slices/2.64 k gates having throughput values of 180/122 Mbps respectively. For high speed KASUMI implementation, the optimized combinational logic methdodology of compact architecture is extended to individual S9/S7 substitution functions and 2 × pipeline schemes are proposed. The odd and even round functions FO and FL are configured for simultaneous operations and path delays are reduced using XOR logic modifications thereby producing high throughput and high efficiency values. Hardware implementations yielded an area of 1619 CLB slices/52.7 k gates attaining throughput values of 16.9/16.1 Gbps for high speed KASUMI architecture I whereas KASUMI architecture II constituted 1847 CLB slices/59.8 k gates attaining very high throughput of 27.5/26.6 Gbps with FPGA and ASICs respectively. A detailed design and performance analysis of proposed KASUMI architectures is described.