Complementary Energy Path Adiabatic Logic-Based Adder Design in 32 Nm FinFET Technology

In most of digital signal processing application, processing elements like adders form the basic building blocks of filtering and analysis of signals. CMOS-based adder circuits suffer from several problems like leakage current and threshold voltage variations. In this paper, a novel design of an adiabatic FinFET-based low-power processing element using complementary energy path adiabatic logic (CEPAL) in 32 nm technology is proposed. The proposed processing elements are CEPAL–FinFET-based adiabatic half adder and full adder. FinFET-based circuits are designed for deep submicron VLSI designs in signal and image applications. The FinFET design has low power consumption when combined with adiabatic design which improves scalability and design flexibility. The proposed FinFET–CEPAL-based adders show a considerable power reduction and low energy consumption with favorable performance improvement. Extensive circuit simulation has been carried out with HSPICE using predictive technology model in 32 nm FinFET technology. The analytical results validate that the proposed design exhibits the energy saving compared to standard bulk CMOS design.