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2010 | OriginalPaper | Buchkapitel

5. DAC Correction and Flexibility, Classification, New Methods and Designs

verfasst von : Georgi Radulov, Patrick Quinn, Hans Hegt, Arthur van Roermund

Erschienen in: Analog Circuit Design

Verlag: Springer Netherlands

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Abstract

This paper classifies correction methods for current-steering Digital-to-Analog Converters (DACs), with an emphasis on self-calibration. Based on this classification, missing methods are identified. Three new DAC correction methods are proposed that can fill in these gaps: high-level mapping, suppression of HD, and calibration of binary currents. All three of them are based on parallel sub-DACs. The paper also proposes to further exploit the advantages of using such parallel sub-DACs to achieve flexibility. Two test-chip implementations in 250 and 180 nm CMOS validate the proposed concepts.

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Literatur
1.
Zurück zum Zitat A. R. Bugeja, B. S. Song, P. L. Rakers, and S. F. Gillig, “A 14-b, 100-MS/s CMOS DAC designed for spectral performance,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 1719–1732, 1999.CrossRef A. R. Bugeja, B. S. Song, P. L. Rakers, and S. F. Gillig, “A 14-b, 100-MS/s CMOS DAC designed for spectral performance,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 1719–1732, 1999.CrossRef
2.
Zurück zum Zitat M. Clara, W. Klatzer, D. Gruber, A. Marak, B. Seger, and W. Pribyl, “A 1.5 V 13bit 130–300MS/s self-calibrated DAC with active output stage and 50 MHz signal bandwidth in 0.13μm CMOS,” in ESSCIRC 2008 Solid-State Circuits Conference, 2008. 34th European, pp. 262–265, 2008. M. Clara, W. Klatzer, D. Gruber, A. Marak, B. Seger, and W. Pribyl, “A 1.5 V 13bit 130–300MS/s self-calibrated DAC with active output stage and 50 MHz signal bandwidth in 0.13μm CMOS,” in ESSCIRC 2008 Solid-State Circuits Conference, 2008. 34th European, pp. 262–265, 2008.
3.
Zurück zum Zitat P. Sungkyung, K. Gyudong, P. Sin-Chong, and K. Wonchan, “A digital-to-analog converter based on differential-quad switching,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1335–1338, 2002.CrossRef P. Sungkyung, K. Gyudong, P. Sin-Chong, and K. Wonchan, “A digital-to-analog converter based on differential-quad switching,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1335–1338, 2002.CrossRef
4.
Zurück zum Zitat C.-H. Lin, F. van der Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, and K. Bult, “A 12b 2.9GS/s DAC with IM3 < − 60dBc Beyond 1 GHz in 65 nm CMOS,” in Solid-State Circuits Conference, 2009. Digest of Technical Papers. ISSCC. 2009 IEEE International, 2009. C.-H. Lin, F. van der Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, and K. Bult, “A 12b 2.9GS/s DAC with IM3 < − 60dBc Beyond 1 GHz in 65 nm CMOS,” in Solid-State Circuits Conference, 2009. Digest of Technical Papers. ISSCC. 2009 IEEE International, 2009.
5.
Zurück zum Zitat G. I. Radulov, P. J. Quinn, H. Hegt, and A. van Roermund, “An on-chip self-calibration method for current mismatch in D/A converters,” in Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European, pp. 169–172, 2005. G. I. Radulov, P. J. Quinn, H. Hegt, and A. van Roermund, “An on-chip self-calibration method for current mismatch in D/A converters,” in Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European, pp. 169–172, 2005.
6.
Zurück zum Zitat Y. Cong and R. L. Geiger, “A 1.5-V 14-bit 100-MS/s self-calibrated DAC,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2051–2060, 2003.CrossRef Y. Cong and R. L. Geiger, “A 1.5-V 14-bit 100-MS/s self-calibrated DAC,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2051–2060, 2003.CrossRef
7.
Zurück zum Zitat K. Doris, “High-speed D/A converters: from analysis and synthesis concepts to IC implementation,” in Eindhoven University of Technology, Faculty of Electrical Engineering. vol. Ph.D. thesis degree Eindhoven: Eindhoven University of Technology, 2004. K. Doris, “High-speed D/A converters: from analysis and synthesis concepts to IC implementation,” in Eindhoven University of Technology, Faculty of Electrical Engineering. vol. Ph.D. thesis degree Eindhoven: Eindhoven University of Technology, 2004.
8.
Zurück zum Zitat P. Harpe, J. M. Meulmeester, A. J. Hegt, and A. van Roermund, “Novel digital pre-correction method for mismatch in DACs with built-in-self measurement,” Proceedings of IEEE ADDA 2005, 2005. P. Harpe, J. M. Meulmeester, A. J. Hegt, and A. van Roermund, “Novel digital pre-correction method for mismatch in DACs with built-in-self measurement,” Proceedings of IEEE ADDA 2005, 2005.
9.
Zurück zum Zitat L. R. Carley and J. Kenney, “A 16-bit 4 ′ τη order noise-shaping D/A converter,” in Custom Integrated Circuits Conference, 1988, Proceedings of the IEEE 1988, pp. 21.7/1–21.7/4, 1988. L. R. Carley and J. Kenney, “A 16-bit 4 τη order noise-shaping D/A converter,” in Custom Integrated Circuits Conference, 1988, Proceedings of the IEEE 1988, pp. 21.7/1–21.7/4, 1988.
10.
Zurück zum Zitat K. L. Chan, N. Rakuljic, and I. Galton, “Segmented dynamic element matching for high-resolution digital-to-analog conversion,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, pp. 3383–3392, 2008.CrossRef K. L. Chan, N. Rakuljic, and I. Galton, “Segmented dynamic element matching for high-resolution digital-to-analog conversion,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, pp. 3383–3392, 2008.CrossRef
11.
Zurück zum Zitat G. R. Spalding and R. L. Geiger, “Digital correction for improved spectral response in signal generation systems,” in 1993 IEEE International Symposium on Circuits and Systems, ISCAS ‘93, pp. 132–135, 1993. G. R. Spalding and R. L. Geiger, “Digital correction for improved spectral response in signal generation systems,” in 1993 IEEE International Symposium on Circuits and Systems, ISCAS ‘93, pp. 132–135, 1993.
12.
Zurück zum Zitat E. Lopelli, J. D. van der Tang, and A. H. M. van Roermund, “A 1 mA ultra-low-power FHSS TX front-end utilizing direct modulation with digital pre-distortion,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 2212–2223, 2007.CrossRef E. Lopelli, J. D. van der Tang, and A. H. M. van Roermund, “A 1 mA ultra-low-power FHSS TX front-end utilizing direct modulation with digital pre-distortion,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 2212–2223, 2007.CrossRef
13.
Zurück zum Zitat S. Ouzounov, E. Roza, J. A. Hegt, G. van der Weide, and A. H. M. van Roermund, “A CMOS V-I converter with 75-dB SFDR and 360-&mu;W power consumption,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1527–1532, 2005.CrossRef S. Ouzounov, E. Roza, J. A. Hegt, G. van der Weide, and A. H. M. van Roermund, “A CMOS V-I converter with 75-dB SFDR and 360-&mu;W power consumption,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1527–1532, 2005.CrossRef
14.
Zurück zum Zitat E. Mensink, E. A. M. Klumperink, and B. Nauta, “Distortion cancellation by polyphase multipath circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, pp. 1785–1794, 2005.CrossRef E. Mensink, E. A. M. Klumperink, and B. Nauta, “Distortion cancellation by polyphase multipath circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, pp. 1785–1794, 2005.CrossRef
15.
Zurück zum Zitat K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, and A. van Roermund, “A 12b 500MS/s DAC with > 70 dB SFDR up to 120 MHz in 0.18um CMOS,” in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, 2005. K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, and A. van Roermund, “A 12b 500MS/s DAC with > 70 dB SFDR up to 120 MHz in 0.18um CMOS,” in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, 2005.
16.
Zurück zum Zitat T. Chen, P. Geens, G. Van der Plas, W. Dehaene, and G. Gielen, “A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL,” in Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, 2004. T. Chen, P. Geens, G. Van der Plas, W. Dehaene, and G. Gielen, “A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL,” in Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, 2004.
17.
Zurück zum Zitat T. Yongjian, H. Hegt, A. van Roermund, K. Doris, and J. Briaire, “Statistical analysis of mapping technique for timing error correction in current-steering DACs,” in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, pp. 1225–1228, 2007. T. Yongjian, H. Hegt, A. van Roermund, K. Doris, and J. Briaire, “Statistical analysis of mapping technique for timing error correction in current-steering DACs,” in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, pp. 1225–1228, 2007.
18.
Zurück zum Zitat G. I. Radulov, P. J. Quinn, J. A. Hegt, and A. H. M. van Roermund, “A start-up calibration method for generic current-steering D/A converters with optimal area solution,” in ISCAS 2005. IEEE International Symposium on Circuits and Systems, 2005, vol. 1, pp. 788–791, 2005. G. I. Radulov, P. J. Quinn, J. A. Hegt, and A. H. M. van Roermund, “A start-up calibration method for generic current-steering D/A converters with optimal area solution,” in ISCAS 2005. IEEE International Symposium on Circuits and Systems, 2005, vol. 1, pp. 788–791, 2005.
19.
Zurück zum Zitat A. R. Bugeja and S. Bang-Sup, “A self-trimming 14-b 100-MS/s CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1841–1852, 2000.CrossRef A. R. Bugeja and S. Bang-Sup, “A self-trimming 14-b 100-MS/s CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1841–1852, 2000.CrossRef
20.
Zurück zum Zitat H. Qiuting, P. A. Francese, C. Martelli, and J. Nielsen, “A 200MS/s 14b 97 mW DAC in 0.18/spl mu/m CMOS,” in Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, pp. 364–532, 2004. H. Qiuting, P. A. Francese, C. Martelli, and J. Nielsen, “A 200MS/s 14b 97 mW DAC in 0.18/spl mu/m CMOS,” in Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, pp. 364–532, 2004.
21.
Zurück zum Zitat M. Clara, W. Klatzer, B. Seger, A. Di Giandomenico, and L. Gori, “A 1.5 V 200MS/s 13b 25 mW DAC with randomized nested background calibration in 0.13/spl mu/m CMOS,” in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 250–600, 2007. M. Clara, W. Klatzer, B. Seger, A. Di Giandomenico, and L. Gori, “A 1.5 V 200MS/s 13b 25 mW DAC with randomized nested background calibration in 0.13/spl mu/m CMOS,” in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 250–600, 2007.
22.
Zurück zum Zitat G. Radulov, P. Quinn, A. J. Hegt, and A. van Roermund, “Method and apparatus for calibrating a scaled current electronic circuit,” in US Patent 7,466,252: Xilinx, 2008. G. Radulov, P. Quinn, A. J. Hegt, and A. van Roermund, “Method and apparatus for calibrating a scaled current electronic circuit,” in US Patent 7,466,252: Xilinx, 2008.
23.
Zurück zum Zitat M. P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 1144–1147, 2001.CrossRef M. P. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 1144–1147, 2001.CrossRef
24.
Zurück zum Zitat G. I. Radulov, P. J. Quinn, P. Harpe, H. Hegt, and A. van Roermund, “Parallel current-steering D/A Converters for Flexibility and Smartness,” in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 1465–1468, 2007. G. I. Radulov, P. J. Quinn, P. Harpe, H. Hegt, and A. van Roermund, “Parallel current-steering D/A Converters for Flexibility and Smartness,” in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 1465–1468, 2007.
Metadaten
Titel
DAC Correction and Flexibility, Classification, New Methods and Designs
verfasst von
Georgi Radulov
Patrick Quinn
Hans Hegt
Arthur van Roermund
Copyright-Jahr
2010
Verlag
Springer Netherlands
DOI
https://doi.org/10.1007/978-90-481-3083-2_5

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