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Erschienen in:
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections Kapitel lesen Erstes Kapitel lesen

2011 | OriginalPaper | Buchkapitel

8. Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

verfasst von : Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli

Erschienen in: Low Power Networks-on-Chip

Verlag: Springer US

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Abstract

Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores that are not used in an application can be shutdown, while the other islands can still be operational. When one or more of the islands are shutdown, the interconnect should allow the communication between islands that are operational. For this, the NoCs has to be designed efficiently to allow shutdown of VIs, thereby reducing the leakage power consumption. In this chapter, we present methods to design NoC topologies that provide such a support for both 2D and 3D ICs. We show how the concept of VIs need to be considered during topology synthesis phase itself. We also make studies to show the benefits of migrating to 3D-stacked chips for realistic applications that have multiple VIs.

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Vorheriges Kapitel Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study
Nächstes Kapitel CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study
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Metadaten
Titel
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
verfasst von
Ciprian Seiculescu
Srinivasan Murali
Luca Benini
Giovanni De Micheli
Copyright-Jahr
2011
Verlag
Springer US
Buch
Low Power Networks-on-Chip

Print ISBN: 978-1-4419-6910-1

Electronic ISBN: 978-1-4419-6911-8

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4419-6911-8_8

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