Design and Performance Investigation of Dual-Gate ZnO Nanostructured Thin-Film Transistor

In this paper, a design and analysis of dual-gate zinc oxide nanostructured thin-film transistors (DG ZnO TFTs) are presented that outperform traditional top-gate (TG) and bottom-gate (BG) ZnO TFTs. TFTs using dual-gate (DG) technology have two conduction channels at each interface (top and bottom) to enhance gate electric fields and effective channel conduction. The capacitive coupling between the top- and bottom-gate dielectrics in the DG ZnO TFTs significantly enhances the surface potential, electric field, and mobility. The DG ZnO TFT exhibits a high drive-ON current (I_ON) of 11.23 mA and a steeper subthreshold swing of 64 mV/dec. The I_ON of the DG ZnO TFT is 58% higher than the sum of the I_ON of the TG and BG ZnO TFTs. We also investigated the impact of channel thickness and dielectric constant of the gate oxide on the electrical performance of the proposed device. The I_ON increases with the decrease of channel thickness and improves with the high dielectric constant of the oxide. When the ZnO channel thickness is 10 nm, and the dielectric is TiO₂, the proposed device exhibits a higher ON current of 178.14 mA.