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Erschienen in:
1996 | OriginalPaper | Buchkapitel
Design for Reuse
verfasst von : Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines
Erschienen in: Quick-Turnaround ASIC Design in VHDL
Verlag: Springer US
Enthalten in: Professional Book Archive
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This chapter starts with an introduction to the core-based DfR/DwR methodology proposed in this monograph. The issues involved in defining an efficient reuse-based design environment are investigated and defined. Later sections describe the different design views that constitute the proposed design methodology. A cost model that compares the relative costs for proposed and existing approaches to ASIC design is also presented.