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Erschienen in: Real-Time Systems 2/2019

16.11.2018

Uneven memory regulation for scheduling IMA applications on multi-core platforms

verfasst von: Muhammad Ali Awan, Pedro F. Souto, Benny Akesson, Konstantinos Bletsas, Eduardo Tovar

Erschienen in: Real-Time Systems | Ausgabe 2/2019

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Abstract

The adoption of multi-cores for mixed-criticality systems has fueled research on techniques for providing scheduling isolation guarantees to applications of different criticalities. These are especially hard to provide in the presence of contention in shared resources of the system, such as buses and DRAMs. The state-of-the-art Single-Core Equivalence (SCE) framework improves timing isolation by enforcing periodic memory access budgets per core, which allows computing safe stall delays for the cores as input to the schedulability analysis. In this work, we extend the theoretical toolkit for this state-of-the-art framework by considering EDF and server-based scheduling, instead of partitioned fixed-priority scheduling which SCE has assumed so far. A second extension to the theory of SCE consists in additionally allowing memory access budgets to be uneven and defined on a per-server basis, rather than just on a per-core basis, which is what was supported until now. This added flexibility allows better memory bandwidth efficiency, especially when servers with dissimilar memory access requirements co-exist on a given core, and this in turn improves schedulability. Finally, we also formulate an Integer-Linear Programming Model (ILP) guaranteed to find a feasible mapping of a given set of servers to processors, including their execution time and memory access budgets, if such a mapping exists. Our experiments with synthetic task sets confirm that considerable improvement in schedulability can result from the use of per-server memory access budgets under the SCE framework.

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Fußnoten
1
For example, one could alternatively consider partitioning the cache among the tasks without locking their pages in place, but instead allowing the cache partitions to be populated dynamically.
 
2
With Fixed-Priority Scheduling, designers sometimes have to artificially shorten periods to make them harmonic, to match EDF’s utilisation bound, however this still entails performance loss, from the artificial task utilisation increase.
 
3
In Mancuso et al. (2015) and Yao et al. (2016) the stall analysis implicitly assumes no preemption. However, by using the concept of a synthetic equivalent task, comprising the task under analysis as well as higher priority tasks, the schedulability analysis is valid regardless of whether or not there are preemptions.
 
4
We start the numbering of lemmas at 0, so that lemmas corresponding to those in Mancuso et al. (2015) have matching numbers.
 
5
We do not know whether there is a closed-form expression for function \(f(K_k)\).
 
6
For simplicity, we use equally spaced samples in a given interval. However, our approach does not depend on this assumption and will work with any set of input samples (integers) within a given interval.
 
7
The memory bandwidth is equally divided among cores and stall analysis is performed through our proposed approach.
 
8
For the parameter set values used in our experiments, most applications with tasks whose utilisation is greater than 0.5 cannot be scheduled on a single core, even when allocated the full memory bandwidth.
 
9
The progressive lockdown curve of the tracking application in Mancuso et al. (2015) shows that 18 locked-down pages offer the best trade-off against the WCET in isolation. The ratio of residual memory accesses (1067882) to the WCET in isolation (\(133,989.029\,\mu \)s) at this point gives \(\varXi =7.97\)\(\mu s^{-1}\).
 
Literatur
Zurück zum Zitat Avionics Application Software Standard Interface, Part 1, Required Services, ARINC SPECIFICATION653P1-3 ed., AERONAUTICAL RADIO, INC. (2010) Avionics Application Software Standard Interface, Part 1, Required Services, ARINC SPECIFICATION653P1-3 ed., AERONAUTICAL RADIO, INC. (2010)
Zurück zum Zitat Baruah S, Burns A (2006) Sustainable scheduling analysis. In: Proceedings of the 27th IEEE real-time systems symposium. pp 159–168 Baruah S, Burns A (2006) Sustainable scheduling analysis. In: Proceedings of the 27th IEEE real-time systems symposium. pp 159–168
Zurück zum Zitat Baruah S, Mok A, Rosier L (1990) Preemptively scheduling hard-real-time sporadic tasks on one processor. In: Proceedings of the 11th IEEE real-time systems symposium Baruah S, Mok A, Rosier L (1990) Preemptively scheduling hard-real-time sporadic tasks on one processor. In: Proceedings of the 11th IEEE real-time systems symposium
Zurück zum Zitat Behnam M, Inam R, Nolte T, Sjödin M (2013) Multi-core composability in the face of memory-bus contention. ACM SIGBED Rev. 10(3):35–42CrossRef Behnam M, Inam R, Nolte T, Sjödin M (2013) Multi-core composability in the face of memory-bus contention. ACM SIGBED Rev. 10(3):35–42CrossRef
Zurück zum Zitat Bini E, Buttazzo G (2009) Measuring the performance of schedulability tests. J Real-Time Syst 30(1–2):129–154MATH Bini E, Buttazzo G (2009) Measuring the performance of schedulability tests. J Real-Time Syst 30(1–2):129–154MATH
Zurück zum Zitat Brandenburg B (2011) Scheduling and locking in multiprocessor real-time operating systems. Ph.D. Dissertation, Department of Computer Science University of North Carolina at Chapel Hill Brandenburg B (2011) Scheduling and locking in multiprocessor real-time operating systems. Ph.D. Dissertation, Department of Computer Science University of North Carolina at Chapel Hill
Zurück zum Zitat Certification authorities software team (cast), position paper (cast-32) multicore processors, Certification authorities in North and South America, Europe, and Asia (2014) Certification authorities software team (cast), position paper (cast-32) multicore processors, Certification authorities in North and South America, Europe, and Asia (2014)
Zurück zum Zitat Davis RI, Burns A (2009) Priority assignment for global fixed priority pre-emptive scheduling in multiprocessor real-time systems. In: Proceedings of the 30th IEEE Real-Time Systems Symposium. pp 398–409 Davis RI, Burns A (2009) Priority assignment for global fixed priority pre-emptive scheduling in multiprocessor real-time systems. In: Proceedings of the 30th IEEE Real-Time Systems Symposium. pp 398–409
Zurück zum Zitat Flodin J, Lampka K, Yi W, (2014) Dynamic budgeting for settling dram contention of co-running hard and soft real-time tasks. In: 2014 9th IEEE International Symposium on Industrial Embedded Systems (SIES). pp 151–159 Flodin J, Lampka K, Yi W, (2014) Dynamic budgeting for settling dram contention of co-running hard and soft real-time tasks. In: 2014 9th IEEE International Symposium on Industrial Embedded Systems (SIES). pp 151–159
Zurück zum Zitat Inam R, Mahmud N, Behnam M, Nolte T, Sjodin M (2014) Multi-core composability in the face of memory-bus contention. In: Applications symposium Inam R, Mahmud N, Behnam M, Nolte T, Sjodin M (2014) Multi-core composability in the face of memory-bus contention. In: Applications symposium
Zurück zum Zitat Liu J (2000) Real-time systems. Prentice Hall, New Jersey Liu J (2000) Real-time systems. Prentice Hall, New Jersey
Zurück zum Zitat Mancuso R, Dudko R, Betti E, Cesati M, Caccamo M, Pellizzoni R (2013) Real-time cache management framework for multi-core architectures. In: 19th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). pp 45–54 Mancuso R, Dudko R, Betti E, Cesati M, Caccamo M, Pellizzoni R (2013) Real-time cache management framework for multi-core architectures. In: 19th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). pp 45–54
Zurück zum Zitat Mancuso R, Pellizzoni R, Caccamo M, Sha L, Yun H (2015) WCET(m) estimation in multi-core systems using single core equivalence. In: Proceedings of the 27th Euromicro conference on real-time systems. pp 174–183 Mancuso R, Pellizzoni R, Caccamo M, Sha L, Yun H (2015) WCET(m) estimation in multi-core systems using single core equivalence. In: Proceedings of the 27th Euromicro conference on real-time systems. pp 174–183
Zurück zum Zitat Nowotsch J, Paulitsch M, Buhler D, Theiling H, Wegener S, Schmidt M, (July, (2014) Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In: 2014 26th Euromicro conference on IEEE real-time systems (ECRTS). pp 109–118 Nowotsch J, Paulitsch M, Buhler D, Theiling H, Wegener S, Schmidt M, (July, (2014) Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In: 2014 26th Euromicro conference on IEEE real-time systems (ECRTS). pp 109–118
Zurück zum Zitat Pellizzoni R, Yun H (2016) Memory servers for multicore systems. In: 2016 IEEE real-time and embedded technology and applications symposium (RTAS). pp 97–108 Pellizzoni R, Yun H (2016) Memory servers for multicore systems. In: 2016 IEEE real-time and embedded technology and applications symposium (RTAS). pp 97–108
Zurück zum Zitat RTCA, Inc. (2005) Integrated Modular Avionics (IMA) Development Guidance and Certification Considerations. U.S. Dept. of Transportation, Federal Aviation Administration RTCA, Inc. (2005) Integrated Modular Avionics (IMA) Development Guidance and Certification Considerations. U.S. Dept. of Transportation, Federal Aviation Administration
Zurück zum Zitat RTCA, Inc. (2012) RTCA/DO-178C. U.S. Dept. of Transportation, Federal Aviation Administration RTCA, Inc. (2012) RTCA/DO-178C. U.S. Dept. of Transportation, Federal Aviation Administration
Zurück zum Zitat RTCA, Inc. (2012) RTCA/DO-254. U.S. Dept. of Transportation, Federal Aviation Administration RTCA, Inc. (2012) RTCA/DO-254. U.S. Dept. of Transportation, Federal Aviation Administration
Zurück zum Zitat Sha L, Caccamo M, Mancuso R, Kim J-E, Yoon M-K, Pellizzoni R, Yun H, Kegley R, Perlman D, Arundale G, Richard B et al (2014) Single core equivalent virtual machines for hard realtime computing on multicore processors. Univ. Tech. Rep, Urbana Champaign Sha L, Caccamo M, Mancuso R, Kim J-E, Yoon M-K, Pellizzoni R, Yun H, Kegley R, Perlman D, Arundale G, Richard B et al (2014) Single core equivalent virtual machines for hard realtime computing on multicore processors. Univ. Tech. Rep, Urbana Champaign
Zurück zum Zitat Sousa PB, Bletsas K, Tovar E, Souto P, Åkesson B (2014) Unified overhead-aware schedulability analysis for slot-based task-splitting. J Real Time Syst 50(5–6):680–735CrossRefMATH Sousa PB, Bletsas K, Tovar E, Souto P, Åkesson B (2014) Unified overhead-aware schedulability analysis for slot-based task-splitting. J Real Time Syst 50(5–6):680–735CrossRefMATH
Zurück zum Zitat Souto P, Sousa P, Davis R, Bletsas K, Tovar E (2015) Overhead-aware schedulability evaluation of semi-partitioned real-time schedulers. In: Proceedings of the 21st IEEE conference on embedded and real-time computing and applications. pp 110–121 Souto P, Sousa P, Davis R, Bletsas K, Tovar E (2015) Overhead-aware schedulability evaluation of semi-partitioned real-time schedulers. In: Proceedings of the 21st IEEE conference on embedded and real-time computing and applications. pp 110–121
Zurück zum Zitat Yao G, Yun H, Wu ZP, Pellizzoni R, Caccamo M, Sha L (2016) Schedulability analysis for memory bandwidth regulated multicore real-time systems. IEEE Trans Comput 65(2):601–614MathSciNetCrossRefMATH Yao G, Yun H, Wu ZP, Pellizzoni R, Caccamo M, Sha L (2016) Schedulability analysis for memory bandwidth regulated multicore real-time systems. IEEE Trans Comput 65(2):601–614MathSciNetCrossRefMATH
Zurück zum Zitat Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2012) Memory access control in multiprocessor for real-time systems with mixed criticality. In: 2012 24th Euromicro IEEE conference on real-time systems (ECRTS). pp 299–308 Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2012) Memory access control in multiprocessor for real-time systems with mixed criticality. In: 2012 24th Euromicro IEEE conference on real-time systems (ECRTS). pp 299–308
Zurück zum Zitat Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2013) Memguard: memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In: Proceedings of the 19th IEEE real-time and embedded technology and applications symposium, pp 55–64 Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2013) Memguard: memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In: Proceedings of the 19th IEEE real-time and embedded technology and applications symposium, pp 55–64
Zurück zum Zitat Yun H, Mancuso R, Wu Z-P, Pellizzoni R (2014) PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In: Proceedings of the 20th IEEE real-time and embedded technology and applications symposium. pp 155–166 Yun H, Mancuso R, Wu Z-P, Pellizzoni R (2014) PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. In: Proceedings of the 20th IEEE real-time and embedded technology and applications symposium. pp 155–166
Metadaten
Titel
Uneven memory regulation for scheduling IMA applications on multi-core platforms
verfasst von
Muhammad Ali Awan
Pedro F. Souto
Benny Akesson
Konstantinos Bletsas
Eduardo Tovar
Publikationsdatum
16.11.2018
Verlag
Springer US
Erschienen in
Real-Time Systems / Ausgabe 2/2019
Print ISSN: 0922-6443
Elektronische ISSN: 1573-1383
DOI
https://doi.org/10.1007/s11241-018-9322-y

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