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2017 | OriginalPaper | Buchkapitel

E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods

verfasst von : Eshan Singh, Clark Barrett, Subhasish Mitra

Erschienen in: Computer Aided Verification

Verlag: Springer International Publishing

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Abstract

During post-silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs. Bug localization involves identification of a bug trace (a sequence of inputs that activates and detects the bug) and a hardware design block where the bug is located. Existing bug localization practices during post-silicon validation are mostly manual and ad hoc, and, hence, extremely expensive and time consuming. This is particularly true for subtle electrical bugs caused by unexpected interactions between a design and its electrical state. We present E-QED, a new approach that automatically localizes electrical bugs during post-silicon validation. Our results on the OpenSPARC T2, an open-source 500-million-transistor multicore chip design, demonstrate the effectiveness and practicality of E-QED: starting with a failed post-silicon test, in a few hours (9 h on average) we can automatically narrow the location of the bug to (the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops on average for a design with ~1 Million flip-flops) and also obtain the corresponding bug trace. The area impact of E-QED is ~2.5%. In contrast, determining this same information might take weeks (or even months) of mostly manual work using traditional approaches.

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Vorheriges Kapitel Look for the Proof to Find the Program: Decorated-Component-Based Program Synthesis

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We use Quick Error Detection (QED) tests that typically achieve error detection latencies of 1,000 clock cycles or fewer (Lin et al. 2014); however, our approach can work with other tests that achieve similar error detection latencies.

We assume that all interfaces for a design block are in the same clock domain and thus all have the same value of T. This assumption can easily be satisfied by modifying the design partitioning algorithm to continue its recursive descent if the current design block uses more than one clock domain.

As an optimization, in this case, we also run the BMC analysis with the smaller value of T for the block. If this analysis is also inconsistent, it provides a much shorter window in which the bug occurred.

E-QED uses symbolic initial values for FFs. To keep this example simple, we set the initial values of the FFs as shown in Fig. 7.

Note that in our simulation experiments, above (in Sect. 3.1), we used different fixed values of b for different parts of the design. In this section, we allow b to vary but all MISRs use the same value of b.

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Titel: E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods
verfasst von: Eshan Singh
Clark Barrett
Subhasish Mitra
Verlag: Springer International Publishing
Buch: Computer Aided Verification
Print ISBN: 978-3-319-63389-3

Electronic ISBN: 978-3-319-63390-9

Copyright-Jahr: 2017
DOI: https://doi.org/10.1007/978-3-319-63390-9_6

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