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2018 | Buch

Power Management of Modern Processors Kapitel lesen Erstes Kapitel lesen

Energy Efficient High Performance Processors

Recent Approaches for Designing Green High Performance Computing

verfasst von: Dr. Jawad Haj-Yahya, Prof. Avi Mendelson, Prof. Yosi Ben Asher, Prof. Anupam Chattopadhyay

Verlag: Springer Singapore

Buchreihe : Computer Architecture and Design Methodologies

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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Über dieses Buch

This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Power Management of Modern Processors
Abstract
Recent technology advances have resulted in power being the major concern for digital design. In this chapter, we give introduction to power management at modern processors and present the parameters that affect the energy and power of digital circuits. The state of the art in power management methodology is examined and we present energy efficiency metrics, such as the energy delay. We examine how modern processors utilize features, such as clock gating, power gating and DVFS in order to reduce the overall energy consumption of the platform while maintaining high performance. Finally, we present state-of-the-art techniques that are used today in modern processors.
Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, Anupam Chattopadhyay
Chapter 2. Dynamic Optimizations for Energy Efficiency
Abstract
The growing adoption of mobile devices powered by batteries along with the high-power costs in data centers raises the need for energy-efficient computing. Dynamic voltage and frequency scaling is often used by the operating system to balance power performance. However, optimizing for energy efficiency faces multiple challenges such as when dealing with nonsteady state workloads. In this work, we develop DOEE—a novel method that optimizes certain processor features for energy efficiency using user-supplied metrics. The optimization is dynamic, taking into account the runtime characteristics of the workload and the platform. The method instruments monitoring code to search for per-program-phase optimal feature configurations that ultimately improve system energy efficiency. We demonstrate the framework using the LLVM compiler when tuning the Turbo Boost feature on modern Intel Core processors. This implementation improves energy efficiency by up to 23% on SPEC CPU2006 benchmarks, outperforming the energy-efficient firmware algorithm.
Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, Anupam Chattopadhyay
Chapter 3. Power Modeling at High-Performance Computing Processors
Abstract
A detailed analysis of power consumption at low-system levels becomes important as a means for reducing the overall power consumption of a system and in order to gain performance by avoiding thermal hotspots that reduce system’s frequency. This work presents a new power estimation method that allows understanding the contribution of different architectural components on the power breakdown of an application. To demonstrate the usefulness of the new proposed tool and methodology, we choose to examine this new methodology while using modern processor architecture such as the newly released Intel Skylake processor while executing the entire SPEC CPU2006 benchmark suite. This chapter will provide a detailed power and performance characterization report for the SPEC CPU2006 benchmarks, analysis of the data using side-by-side power, and performance breakdowns, as well as few other interesting case studies.
Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, Anupam Chattopadhyay
Chapter 4. Compiler-Directed Energy Efficiency
Abstract
Modern superscalar CPUs contain large complex structures and diverse execution units, consuming wide dynamic power range. Building power delivery network for the worst-case power consumption is not energy efficient and often impossible to fit in small systems. Instantaneous power excursions can cause voltage droops. Power management algorithms are too slow to respond to instantaneous events. In this work, we propose a novel compiler-directed framework to address this problem. The framework is validated on a 4th Generation Intel® Core™ processor and with simulator on output trace. Up to 16% performance speedup is measured over baseline for the SPEC CPU2006 benchmarks.
Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, Anupam Chattopadhyay
Chapter 5. Static Power Modeling for Modern Processor
Abstract
Power and energy estimation tools are essential tools that are used by system designers, software developers, and compiler developers to optimize their products. In this work, we present a novel method for statically estimating and analyzing the energy and power of programs, the method gives power and energy statistics on the feasible program paths for both the core and cache using symbolic execution. Unlike profile-guided optimizations—that require generating stimulus and running them on the target processor to cover all possible paths—or the dataflow analysis that traverse all control flow graph paths, our method traverses all feasible paths of the program. Our method is static, which enables running it at compile-time. We demonstrated how the tool can be used to optimize the power and energy of programs at compile-time by choosing compiler flags that minimize the energy or power of the program.
Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, Anupam Chattopadhyay
Metadaten
Titel
Energy Efficient High Performance Processors
verfasst von
Dr. Jawad Haj-Yahya
Prof. Avi Mendelson
Prof. Yosi Ben Asher
Prof. Anupam Chattopadhyay
Copyright-Jahr
2018
Verlag
Springer Singapore
Electronic ISBN
978-981-10-8554-3
Print ISBN
978-981-10-8553-6
DOI
https://doi.org/10.1007/978-981-10-8554-3

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