Hardware Prototyping for Enhanced Resilient Onboard Navigation Unit

Dependability of safety critical system by fault tolerant design approach use redundant architecture to tolerate hardware faults. Navigation, Guidance and Control units of onboard computers in Indian satellite launch vehicles rely on hot standby dual redundancy. Effective use of computational resources is desirable in such applications where weight, size, power and volume are critical. Resource augmentation based on task criticality can achieve an increased slack margin which further is used for software and transient fault handling and improved system performance. In this paper, design and development of a hardware prototype with fault injection on an LPC 1768 ARM processor, for validating and testing the fault tolerant resource augmented scheduling of onboard computers is presented. The resource augmented system with added flexibility has been evaluated for improved performance and superior management of faults. The system provides better slack margin and resource utilization which leads for tolerating increased number of transient and software faults.