Skip to main content

2010 | OriginalPaper | Buchkapitel

3. High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters

verfasst von : Hans Van de Vel

Erschienen in: Analog Circuit Design

Verlag: Springer Netherlands

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

High-resolution wide-bandwidth ADCs in nm-CMOS are key enablers in increasing the level of digitization and integration in cellular base station receivers. This paper discusses smart techniques to overcome the limitations of low supply voltage and low intrinsic device gain. A 14 b 100 MS/s ADC in 90 nm CMOS is described demonstrating that good power efficiency can be achieved in nm-CMOS with a low supply voltage.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat B.-G. Lee et al., “A 14 b 100 MS/s Pipelined ADC with a Merged Active S/H and First MDAC”, ISSCC Dig. Tech. Papers, pp. 248–249, Feb. 2008. B.-G. Lee et al., “A 14 b 100 MS/s Pipelined ADC with a Merged Active S/H and First MDAC”, ISSCC Dig. Tech. Papers, pp. 248–249, Feb. 2008.
2.
Zurück zum Zitat A. van Roermund et al., “Smart AD and DA Converters”, Proc. ISCAS, pp. 4062–4065, May 2005. A. van Roermund et al., “Smart AD and DA Converters”, Proc. ISCAS, pp. 4062–4065, May 2005.
3.
Zurück zum Zitat H. Van de Vel, B. Buter, H. van der Ploeg, M. Vertregt, G. Geelen and E. Paulus, “A 1.2 V 250 mW 14b 100MS/s Digitally Calibrated Pipeline ADC in 90 nm CMOS”, VLSI Circuits Symp. Dig., pp. 74–75, Jun. 2008. H. Van de Vel, B. Buter, H. van der Ploeg, M. Vertregt, G. Geelen and E. Paulus, “A 1.2 V 250 mW 14b 100MS/s Digitally Calibrated Pipeline ADC in 90 nm CMOS”, VLSI Circuits Symp. Dig., pp. 74–75, Jun. 2008.
4.
Zurück zum Zitat H. Van de Vel, B.A.J. Buter, H. van der Ploeg, M. Vertregt, G.J.G.M. Geelen and E.J.F. Paulus, “A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS”, IEEE J. Solid-State Circuits, vol. 44, pp. 1047–1056, Apr. 2009.CrossRef H. Van de Vel, B.A.J. Buter, H. van der Ploeg, M. Vertregt, G.J.G.M. Geelen and E.J.F. Paulus, “A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS”, IEEE J. Solid-State Circuits, vol. 44, pp. 1047–1056, Apr. 2009.CrossRef
5.
Zurück zum Zitat S.H. Lewis and P.R. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter”, IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.CrossRef S.H. Lewis and P.R. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter”, IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.CrossRef
6.
Zurück zum Zitat W. Yang et al., “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input”, IEEE J. Solid-State Circuits, vol. 36, pp. 1931–1936, Dec. 2001.CrossRef W. Yang et al., “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input”, IEEE J. Solid-State Circuits, vol. 36, pp. 1931–1936, Dec. 2001.CrossRef
7.
Zurück zum Zitat P. Bogner et al., “A 14 b 100 MS/s Digitally Self-Calibrated Pipelined ADC in 0. 13 μm CMOS”, ISSCC Dig. Tech. Papers, pp. 832–833, Feb. 2006. P. Bogner et al., “A 14 b 100 MS/s Digitally Self-Calibrated Pipelined ADC in 0. 13 μm CMOS”, ISSCC Dig. Tech. Papers, pp. 832–833, Feb. 2006.
8.
Zurück zum Zitat B. Murmann and B.E. Boser, “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”, IEEE J. Solid-State Circuits, vol. 38, pp. 2040–2050, Dec. 2003.CrossRef B. Murmann and B.E. Boser, “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”, IEEE J. Solid-State Circuits, vol. 38, pp. 2040–2050, Dec. 2003.CrossRef
9.
Zurück zum Zitat J.K. Fiorenza et al., “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies”, IEEE J. Solid-State Circuits, vol. 41, pp. 2658–2668, Dec. 2006.CrossRef J.K. Fiorenza et al., “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies”, IEEE J. Solid-State Circuits, vol. 41, pp. 2658–2668, Dec. 2006.CrossRef
10.
Zurück zum Zitat M. Anthony, E. Kohler, J. Kurtze, L. Kushner and G. Sollner, “A Process-Scalable Low-Power Charge-Domain 13-bit Pipeline ADC”, VLSI Circuits Symp. Dig., pp. 222–223, Jun. 2008. M. Anthony, E. Kohler, J. Kurtze, L. Kushner and G. Sollner, “A Process-Scalable Low-Power Charge-Domain 13-bit Pipeline ADC”, VLSI Circuits Symp. Dig., pp. 222–223, Jun. 2008.
11.
Zurück zum Zitat B. Murmann, “A/D Converter Trends: Power Dissipation, Scaling and Digitally Assisted Architectures”, Proc. CICC, pp. 105–112, Sep. 2008. B. Murmann, “A/D Converter Trends: Power Dissipation, Scaling and Digitally Assisted Architectures”, Proc. CICC, pp. 105–112, Sep. 2008.
12.
Zurück zum Zitat B.-S. Song, S.-H. Lee and M.F. Tompsett, “A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter”, IEEE J. Solid-State Circuits, vol. 25, pp. 1328–1338, Dec. 1990.CrossRef B.-S. Song, S.-H. Lee and M.F. Tompsett, “A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter”, IEEE J. Solid-State Circuits, vol. 25, pp. 1328–1338, Dec. 1990.CrossRef
13.
Zurück zum Zitat A.N. Karanicolas et al., “A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC”, IEEE J. Solid-State Circuits, vol. 28, pp. 1207–1215, Dec. 1993.CrossRef A.N. Karanicolas et al., “A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC”, IEEE J. Solid-State Circuits, vol. 28, pp. 1207–1215, Dec. 1993.CrossRef
14.
Zurück zum Zitat I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters”, IEEE Trans. Circuits and Systems II, pp. 185–196, Mar. 2000. I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters”, IEEE Trans. Circuits and Systems II, pp. 185–196, Mar. 2000.
15.
Zurück zum Zitat P. Wambacq and W. Sansen, “Distortion Analysis of Analog Integrated Circuits”, Kluwer, 1998. P. Wambacq and W. Sansen, “Distortion Analysis of Analog Integrated Circuits”, Kluwer, 1998.
16.
Zurück zum Zitat K. Bult, “Analog Design in Deep Sub-Micron CMOS”, Proc. ESSCIRC, pp. 126–132, Sep. 2000. K. Bult, “Analog Design in Deep Sub-Micron CMOS”, Proc. ESSCIRC, pp. 126–132, Sep. 2000.
17.
Zurück zum Zitat A.-J. Annema, B. Nauta, R. van Langevelde and H. Tuinhout, “Analog Circuits in Ultra-Deep-Submicron CMOS”, IEEE J. Solid-State Circuits, vol. 40, pp. 132–143, Jan. 2005.CrossRef A.-J. Annema, B. Nauta, R. van Langevelde and H. Tuinhout, “Analog Circuits in Ultra-Deep-Submicron CMOS”, IEEE J. Solid-State Circuits, vol. 40, pp. 132–143, Jan. 2005.CrossRef
18.
Zurück zum Zitat S. Limotyrakis, S.D. Kulchycki, D.K. Su and B.A. Wooley, “A 150-MS/s 8-b 71-mW CMOS Time-Interleaved ADC”, IEEE J. Solid-State Circuits, vol. 40, pp. 1057–1067, May 2005.CrossRef S. Limotyrakis, S.D. Kulchycki, D.K. Su and B.A. Wooley, “A 150-MS/s 8-b 71-mW CMOS Time-Interleaved ADC”, IEEE J. Solid-State Circuits, vol. 40, pp. 1057–1067, May 2005.CrossRef
19.
Zurück zum Zitat Y. Chiu, P.R. Gray and B. Nikolic, “A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR”, IEEE J. Solid-State Circuits, vol. 39, pp. 2139–2151, Dec. 2004.CrossRef Y. Chiu, P.R. Gray and B. Nikolic, “A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR”, IEEE J. Solid-State Circuits, vol. 39, pp. 2139–2151, Dec. 2004.CrossRef
Metadaten
Titel
High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters
verfasst von
Hans Van de Vel
Copyright-Jahr
2010
Verlag
Springer Netherlands
DOI
https://doi.org/10.1007/978-90-481-3083-2_3

Neuer Inhalt