Investigation of Device and Circuit-Level Performances of Dielectric Engineered Dopingless SOI Schottky Barrier MOSFET

In this work, we have represented a simulation study that includes the device and circuit-level performance improvements of SOI Schottky barrier (SB) MOSFETs. We have introduced the charge plasma concept instead of physical doping in our proposed SB-MOSFET. The gate work function (WF) engineering realizes the dopant segregation layers near the source and drains regions of the gate electrode. The WF near the source side charge plasma (CP) metal is optimized to improve the I_ON while the WF of the CP metal near the drain side is kept fixed. Dielectric engineering has been performed to minimize the leakage current. The gate dielectric (HfO₂) with high-k permittivity is used on the source side to induce high gate dielectric capacitance density and that will create the electron accumulation near the source end at the channel. The length of the gate dielectric (SiO₂) with low-k permittivity near the drain side is optimized to minimize the ambipolar current. The analog/RF performance parameters are investigated and compared to the conventional SOI SB-MOSFET. The simulation result indicates that there is a remarkable improvement in transconductance (58%) and cut-off frequency (87%) of the proposed dielectric engineered CP-based SOI SB-MOSFET (DE-CP-SOI-SB-MOSFET) than the SOI SB-MOSFET. Verilog-A model-based N-MOS inverters are simulated and analyzed to investigate the switching performance of two devices. It has been found that the average switching delay and the power delay product (PDP) have improved by 60 times and 36%, respectively, in the proposed DE-CP-SOI-SB-MOSFET-based inverter than the conventional SOI SB-MOSFET-based inverter.