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Journal of Computational Electronics

Erschienen in:

31.05.2021

A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature

verfasst von: Amir Gavoshani, Ali A. Orouji

Erschienen in: Journal of Computational Electronics | Ausgabe 4/2021

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Abstract

We propose a novel deep gate lateral double diffused metal-oxide-semiconductor (LDMOS) field-effect transistor in partial silicon-on-insulator (PSOI) technology for achieving high breakdown voltage and reduced power dissipation. In the proposed device, an N⁺ well is inserted in the buried oxide under the drain region. By optimizing the N⁺ well and the lateral distance between the buried oxide and the left side of the device, the electric field is modified. Therefore, the breakdown voltage improves. Also, the PSOI technology used in the proposed structure has a significant effect on reducing the lattice temperature. Our simulation results show that the proposed structure improves the breakdown voltage by about 67.5% and reduces the specific on-resistance by about 20% in comparison with a conventional LDMOS.

Vorheriger Artikel Electrostatic characterization and threshold voltage modeling of inversion type InGaAs gate-all-around MOSFET

Nächster Artikel A comparison of swarm-based optimization algorithms in linear antenna array synthesis

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Titel: A novel deep gate power MOSFET in partial SOI technology for achieving high breakdown voltage and low lattice temperature
verfasst von: Amir Gavoshani
Ali A. Orouji
Publikationsdatum: 31.05.2021
Verlag: Springer US
Erschienen in: Journal of Computational Electronics / Ausgabe 4/2021
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI: https://doi.org/10.1007/s10825-021-01724-5

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