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2020 | OriginalPaper | Buchkapitel

3. Body-Bias for Digital Designs

verfasst von : Sylvain Clerc, Ricardo Gomez Gomez

Erschienen in: The Fourth Terminal

Verlag: Springer International Publishing

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Abstract

In this chapter we will detail the key advantages of Body-Bias for digital design. As Body-Bias modulates the transistors’ V T, it enables higher I on at the expense of higher I off. This design tuning knob can be used to either increase yield (more dies within design specifications), or to extend the operating performance (with lower voltage, higher speed, or lower power). Increased yield can be brought directly by die acceleration, while indirect leakage gains can be obtained through increased transistor drive of slowest transistors at slowest process corner. Similarly, indirect dynamic power reduction can be obtained thanks to lower operating voltage. As some of these gains require trade-off, such as increased speed at low temperature vs. higher leakage at maximum temperature, the circuit architect can either find the best trade-off between these aspects and/or implement system operating modes. This chapter describes how to modulate the Body-Bias (i.e., the bias law and the bias limits) from a design perspective to take full advantage of this tuning capability.

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Fußnoten
1
More on this design space evolution with Body-Bias in Chap. 16.
 
2
Further abbreviated qFO4, see Fig. 3.2 and next section for an explanation of quasi-fan-out-of-4 logic path and why we call it ‘quasi’.
 
3
Hence the ‘quasi’ fan-out-of-4.
 
4
The internal energy is the energy driven by the cell with input and output capacitance load energy excluded.
 
5
Implicit bias maximum applied at slowest RTL synthesis PVT, kindly refer to Sect. 16.​3.
 
6
Kindly refer to Chap. 16 for implementation corners definition.
 
7
Because there is a race between the global cell undersize and individual cell leakage, we denote this leakage reduction as ‘indirect’.
 
8
Kindly refer to Appendix B in case you are not familiar with digital constraints.
 
9
Gate overdrive voltage.
 
10
Or else consider AVS, see Chap. 14 (Sect. 14.​1) to review which option is the best for your design.
 
11
In situations of high temp skewed corners, SRAM bitcell has their stability weakened by V T shift induced by Forward Body-Bias, see Chap. 5.
 
12
In FD-SOI V T modulation can be done by transistors WELLs, LVT transistors have their NMOS in NWELL and PMOS is PWELL. Refer to Chap. 2.
 
13
Emphasized for the reader to understand that there is a trade-off to make here.
 
Literatur
1.
Zurück zum Zitat F. Abouzeid, S. Clerc, F. Firmin, M. Renaudin, G. Sicard, A 45nm CMOS 0.35V-optimized standard cell library for ultra-low power applications, in International Symposium On Low Power Electronics and Design (2009) F. Abouzeid, S. Clerc, F. Firmin, M. Renaudin, G. Sicard, A 45nm CMOS 0.35V-optimized standard cell library for ultra-low power applications, in International Symposium On Low Power Electronics and Design (2009)
2.
Zurück zum Zitat F. Abouzeid, C. Bernicot, S. Clerc, J.M. Daveau, G. Gasiot, D. Noblet, D. Soussan, P. Roche, 30% static power improvement on ARM CortexⓇ-A53 using static Biasing-Anticipation, in 2016 46th European Solid-State Device Research Conference (ESSDERC) (2016), pp. 29–32 F. Abouzeid, C. Bernicot, S. Clerc, J.M. Daveau, G. Gasiot, D. Noblet, D. Soussan, P. Roche, 30% static power improvement on ARM Cortex-A53 using static Biasing-Anticipation, in 2016 46th European Solid-State Device Research Conference (ESSDERC) (2016), pp. 29–32
3.
Zurück zum Zitat S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J.M. Daveau, C. Bottoni, D. Bol, J. De-Vos, D. Zamora, B. Coeffic, D. Soussan, D. Croain, M. Naceur, P. Schamberger, P. Roche, D. Sylvester, 8.4 A 0.33V/−40 ∘C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing, in 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers (2015), pp. 1–3 S. Clerc, M. Saligane, F. Abouzeid, M. Cochet, J.M. Daveau, C. Bottoni, D. Bol, J. De-Vos, D. Zamora, B. Coeffic, D. Soussan, D. Croain, M. Naceur, P. Schamberger, P. Roche, D. Sylvester, 8.4 A 0.33V/−40 C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing, in 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers (2015), pp. 1–3
4.
Zurück zum Zitat R.I.M.P. Meijer, Body bias aware digital design, PhD manuscript, Eindhoven University of Technology, 2011 R.I.M.P. Meijer, Body bias aware digital design, PhD manuscript, Eindhoven University of Technology, 2011
5.
Zurück zum Zitat D. Jacquet, F. Hasbani, P. Flatresse, R. Wilson, F. Arnaud, G. Cesana, T.D. Gilio, C. Lecocq, T. Roy, A. Chhabra, C. Grover, O. Minez, J. Uginet, G. Durieu, C. Adobati, D. Casalotto, F. Nyer, P. Menut, A. Cathelin, I. Vongsavady, P. Magarshack, A 3 GHz dual core processor ARM cortex TM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization. IEEE J. Solid-State Circuits 49(4), 812–826 (2014)CrossRef D. Jacquet, F. Hasbani, P. Flatresse, R. Wilson, F. Arnaud, G. Cesana, T.D. Gilio, C. Lecocq, T. Roy, A. Chhabra, C. Grover, O. Minez, J. Uginet, G. Durieu, C. Adobati, D. Casalotto, F. Nyer, P. Menut, A. Cathelin, I. Vongsavady, P. Magarshack, A 3 GHz dual core processor ARM cortex TM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization. IEEE J. Solid-State Circuits 49(4), 812–826 (2014)CrossRef
Metadaten
Titel
Body-Bias for Digital Designs
verfasst von
Sylvain Clerc
Ricardo Gomez Gomez
Copyright-Jahr
2020
DOI
https://doi.org/10.1007/978-3-030-39496-7_3

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