The Fourth Terminal

Fully depleted silicon on insulator (FD-SOI) transistor is a planar device, as used in former CMOS technologies taking advantages of thin silicon film enhancing electrostatic behavior and thin buried oxide providing a back gate option. In this chapter, we are demonstrating the benefit of both process improvements. Significant leakage reduction combined with higher drive is achieved thanks to the fully depleted SOI structure, especially at low voltage operation. On the other hand, the strong efficiency of the forth terminal of the device allowing full forward body-bias (FBB) usage has been established with a reduction of 90% of the active power thanks to a smart V _dd∕V _bb biasing optimization, without any circuit speed degradation. Leveraging the FBB technique to decrease efficiently the threshold voltage of the device, some interesting benefits have been shown for analog blocs such as transconductance (gm) and out voltage gain (gd). Finally, we have been able to evidence the softness of FBB solution improving performance in terms of transistor reliability. No impact on gate oxide dielectric has been observed, neither for the oxide breakdown (the so-called TDDB) and negative bias temperature instability (NBTI) due to the fact that any further overdrive is applied at the front gate of the device. Moreover, no specific hot carrier injection (HCI) degradation has been found with FBB solution thanks to an equivalent lateral electric field. Based on all those results accumulated, we can clearly certify that FBB technique usage in FD-SOI device is fully compatible with advanced CMOS technology node in terms of digital speed, power reduction, mixed signal analog performance, and reliability criteria.

In this chapter we will detail the key advantages of Body-Bias for digital design. As Body-Bias modulates the transistors’ V _T, it enables higher I _on at the expense of higher I _off. This design tuning knob can be used to either increase yield (more dies within design specifications), or to extend the operating performance (with lower voltage, higher speed, or lower power). Increased yield can be brought directly by die acceleration, while indirect leakage gains can be obtained through increased transistor drive of slowest transistors at slowest process corner. Similarly, indirect dynamic power reduction can be obtained thanks to lower operating voltage. As some of these gains require trade-off, such as increased speed at low temperature vs. higher leakage at maximum temperature, the circuit architect can either find the best trade-off between these aspects and/or implement system operating modes. This chapter describes how to modulate the Body-Bias (i.e., the bias law and the bias limits) from a design perspective to take full advantage of this tuning capability.

This chapter introduces the usage of body-bias for analog designs. The benefits of bias tuning knob are first introduced for signal path or trimming elements. From device cross-section, the demonstration of the non-intrusive capability of body-bias is emphasized as it enables V _T modulation with no added series resistance of parasitic capacitance. Similarly to the digital designs, dynamic body-bias can be used to compensate process, voltage, temperature, and aging (PVTA) variations and static bias can be used to augment devices conductance, both cases are discussed in two dedicated sections with reference to detailed chapters in Part II.

This chapter explores how static random-access memory (SRAM) functionality is influenced by application of a Body-Bias voltage. Investigating the SRAM stability is a complex task itself, even without any applied Body-Bias. After a short introduction to yield and why nowadays SRAM stability is the major detractor of silicon yield, the bitcell circuit is presented and its major failure modes are discussed. After further inquiries about how technology specifications about SRAM can be embedded into spice model cards, it is shown how to use the latter to build a yield model under the V _min paradigm, by which a single voltage value is taken as minimum supported operating voltage at each different process and temperature condition, and how the model fits to silicon data. Body-Bias effects on the bitcell are then discussed and the high frequency (HF) functionality is explored with both experimental and theoretical results, leading to a very complex framework that calls for a new paradigm based on the maximum number of instantiation N _max, in order to have an efficient data analysis. This is carried out with the yieldogram tool, that ultimately allows to present Body-Bias effects on the expected, mass-scale production yield of arbitrary amounts of memory, even at HF. This chapter text includes and extends the content of some of the author’s publications (Thomas et al., 2014 IEEE international electron devices meeting, pp 3.4.1–3.4.4, 2014. https://doi.org/10.1109/IEDM.2014.7046973; Ranica et al., 2016 IEEE symposium on VLSI circuits (VLSI-circuits), pp 1–2, 2016. https://​doi.​org/​10.​1109/​VLSIC.​2016.​7573512; Ciampolini et al., 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8, 2016. https://​doi.​org/​10.​1145/​2966986.​2967031; Akyel, Statistical methodologies for modeling the impact of process variability in ultra-deep-submicron SRAMs, PhD manuscript, Université de Grenoble, 2014; Dhori et al., 2017 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT), pp 1–6, 2017. https://​doi.​org/​10.​1109/​DFT.​2017.​8244429; Ciampolini et al., J Low Power Electron 8(1):106, 2012. https://​doi.​org/​10.​1166/​jolpe.​2012.​1175).

This chapter starts by highlighting the requirements and existing techniques in producing digital delay, summarizing the state of the art. Subsequently, a topology assessment is presented based on specified performance metrics. The proposed delay cell which was designed, fabricated, and characterized is then described. Specifically, the proposed design is based on a topology with low-supply-noise sensitivity and low jitter. Functionality is extended to support coarse/fine control for the output delay value, without the need for additional hardware. This is made possible by taking advantage of the body-biasing capabilities available in FD-SOI technology. The proposed delay element presents unique performance characteristics in terms of the achieved delay resolution and delay dynamic range. The chapter concludes with the demonstration of a delay line prototype, fabricated in ST 28 nm FD-SOI technology. After a general overview of delay techniques the proposed topology is described, by focusing on the major design aspects. Measurement results are then presented and a short discussion follows on the characterization findings.

This chapter presents mm-wave distributed oscillators (DOs) design running at 134 and 200 GHz, in 28 nm FD-SOI technology. First, the DO theory for operation close to transistor’s f _T is detailed and then the design of their amplification stage and transmission lines (TLs) in a dedicated section each. The first section gives an insight of body-bias tuning capability through V _T modulation governing the DOs’ output voltage, the two latter sections including layout consideration to minimize parasitics. The measurement setup and measurement results are then presented and a comparison with state of the art ends the chapter. The measured results show a remarkable DC-to-RF efficiency at 5.8% and phase noise of −99 dBc/Hz at 1 MHz offset and body-bias trimming effect on output power, DC-to-RF efficiency, and phase noise is detailed. Variability on wafer was measured for both oscillators, as an example, the 134 GHz oscillator features 0.015% frequency and 0.4 dBm output power standard deviations on 24 locations. Phase noise optimization against DC-to-RF efficiency trade-off using body-bias trimming is presented with 5 dBc/Hz phase noise gain at the limited cost of 1.8% efficiency reduction. This trimming can be adjusted by software configuration according to application needs.

In this chapter, a 31 GHz reconfigurable balanced 2-stage power amplifier (PA) integrated in 28 nm FD-SOI CMOS technology is demonstrated aiming for SoC implementation. Fine grain wide range power gain control with more than 10 dB tuning range is enabled by body-biasing feature while the design improves VSWR robustness, stability, and reverse isolation by using optimized 90^∘ hybrid couplers and capacitive neutralization over both stages. Maximum power gain of 32.6 dB, PAE_max of 25.5%, and P _sat of 17.9 dBm are measured, while robustness to industrial temperature range and process spread is demonstrated. This PA exhibits a maximum ITRS figure of merit of 26,925 which is the highest reported around 30 GHz to authors’ knowledge.

In this chapter, we explore the use of adaptive back biasing to tune RF characteristics in wireless transmitters for ultra-low-power operation. To this end, we design an 802.15.4 impulse-radio (IR) UWB transmitter in 28 nm FD-SOI where back biasing is used to tune (1) the RF carrier frequency to the desired channel and (2) the RF output power to meet the spectral regulations. The transmitter is based on a digital PLL-free architecture for frequency synthesis with a pulse-shaping digital power amplifier. These architectural features combined with the FD-SOI capability to operate the transmitter at ultra-low-voltage (0.55 V) up to 4.5 GHz enable state-of-the art efficiency (2.6%) and extremely low energy per bit (≪1 nJ/bit).

Temperature monitoring is critical to the operation of all SoCs, as it provides information to adjust logic timing, optimize power management, or calibrate analog circuits. The temperature information should be obtained with a fine spatial and temporal resolution, which requires low-area sensors with a fast conversion time. Digital MOS sensors offer such performance and take full advantage of process scaling; however, they often require costly two-point calibration to achieve the desired accuracy. This chapter presents a digital sensor in 28 nm FD-SOI process which takes advantage of the technology’s extended body-biasing capabilities for process compensation. Through an NMOS-only oscillator, a single regulator provides a low-noise supply and NWell biasing. The probe is complemented by an on-chip digital logic backend to compensate for non-linearities. The whole system achieves an accuracy of −1.4 ∘C/1.3 ∘C, a per-probe area of 1044 µm², and accommodates a wide operating range (0.62–1.2 V) and satisfying power (2.0 nJ/Sa) and accuracy.

Improving the energy efficiency of processor systems-on-chip (SoCs) is key to improving their performance and utility. The FD-SOI silicon process enables integrated systems that can deliver dramatic improvements in energy efficiency through system integration. This chapter presents the Raven-3 and Raven-4 testchips, fully integrated and fully featured SoCs which achieve energy-efficient operation with low overhead. RISC-V processors allow for innovation and experimentation in the context of a free, open architecture. Integrated switched-capacitor voltage regulators can achieve high conversion efficiency when coupled with adaptive clock generators. Custom SRAM macros operate at low supply voltages, enabling wide voltage scaling. An integrated body-bias generator allows run-time tuning of threshold voltage for improved performance or reduced leakage. Taken together, these innovations showcase the possibilities of FD-SOI technology.

In this chapter, we present the closed-loop control of the circuit’s timing as a way to regulate the body-bias and compensate for variations. We will go through the main building blocks of closed-loop timing systems, with a special attention to speed monitors, which will be reviewed and commented. To exemplify the closed-loop approach, we will present a regulation system containing a tunable replica circuit (TRC) that compensates the process and temperature variations of a SPARC/LEON3 processor with body-bias.

This section reports open loop Body-Bias control implemented in two designs. The first one is based on a microprocessor hosting bias control hardware and the compensation software, using a C-code look-up table to adjust bias according to temperature via periodic interrupt handler. The second one is based on a full ASIC logic flow and applies a combination of linear laws to achieve voltage and temperature compensation. In both cases, the bias laws are derived from the bias response exposed in Sect. 3.​2. The comparison of both methods is made for the reader to take his decision on which approach best suits his circuit need.

In this chapter we will go through the arbitration of different compensation and regulation systems. To begin with, we will compare the main variation compensation techniques, voltage scaling and body-biasing, by studying their impact on the compensated circuits’ specifications and evaluating their costs and benefits. As an addition, we will include an exploration of the potential advantages of a combination of both. Then, we will compare the closed-loop and open-loop regulation techniques detailed in Chaps. 12 and 13 as a way to modulate the body-bias on chip. We will discuss if it is worth or not investing in a more sophisticated closed-loop to regulate the body-bias over a simpler approach based on an open-loop regulation.

In this chapter we will discuss about the choice of generating body-bias voltage generation inside or outside of the SoCs. For both cases advantages and disadvantages will be highlighted. The second step of this part treats of the load seen by a Body-Bias GENerator (BBGEN), embedded or not. These exercises will be helpful to determine the list of main specifications that should have a BBGEN. Each specification elements will be detailed. As for any analogue circuit, knowledge of the output load is definitely essential to realize a successful design. After that we will elaborate on some way to build and design a BBGEN and how to implement it at SoC level.

This chapter deals with digital static timing analysis and implementation methodology, covering design corners definition, implementation corners selection, power grid with specific aspect added or changed with body-bias.