Low Power and Suppressed Noise 6T, 7T SRAM Cell Using 18 nm FinFET

The fundamental components of maximum digital devices are memories and therefore stability, performance and efficiency of the system can be modified by decreasing the power requirement of memory. SRAM cells have less leakage making them suitable for portable and embedded devices. FinFETs are proven to be a promising candidate with high performance low power consumption features at lower technology nodes. Low power is one of the major concerns of a designer working on semiconductor memories which is possible by transistor leakage current reduction. In this work, a comparative analysis of CMOS, FinFET-based 6T and 7T SRAM cells is performed to obtain low leakage or low static power consumption with the increased value of static noise margin (SNM). It is found that an SRAM cell designed with 18 nm FinFET, has better stability and power handling capability compared to other CMOS-based SRAM’s. A high value of SNM is obtained in the FinFET-based 7T SRAM cell with static power consumption reduced by 20.2% for write ‘0’ process, 15.36% for write ‘1’ process, 18.62% for read ‘0’ process and 22.37% for read ‘1’ process respectively compared to CMOS 7T SRAM. The proposed 7T FinFET SRAM has 2.64 times more Read SNM; 1.082 times more Hold SNM and 1.064 times Write SNM compared to CMOS 7T SRAM. All the designs and simulations are carried out using Cadence Virtuoso ADE.