Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Bücher
Zeitschriften
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
MTZ-Fachkongress

Antriebe und Energiesysteme von morgen


Austausch von Automobil- und Energiewirtschaft

Am 14./15. Mai geht es in Chemnitz um die Mobilitätswende durch Elektro- und Wasserstofffahrzeuge.
Erweiterte Suche
Anmelden
nach oben
Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 3/2012

01.06.2012

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems

verfasst von: Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera

Erschienen in: Journal of Electronic Testing | Ausgabe 3/2012

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

The push to embed reliable and low-power memories architectures into modern systems-on-chip is driving the EDA community to develop new design techniques and circuit solutions that can concurrently optimize aging effects due to Negative Bias Temperature Instability (NBTI), and static power consumption due to leakage mechanisms. While recent works have shown how conventional leakage optimization techniques can help mitigate NBTI-induced aging effects on cache memories, in this paper we focus specifically on scratchpad memory (SPM) and present novel software approaches as a means of alleviating the NBTI-induced aging effects. In particular, we demonstrate how intelligent software directed data allocation strategies can extend the lifetime of partitioned SPMs by means of distributing the idleness across the memory sub-banks.
Vorheriger Artikel IC Immunity Modeling Process Validation Using On-Chip Measurements
Nächster Artikel Challenges for Semiconductor Test Engineering: A Review Paper

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Jetzt informieren
Weitere Produktempfehlungen anzeigen
Fußnoten
1
The granularity of the power-managed units can range from one cell to one word, or groups of adjacent words.
 
2
This term is null for both the vanilla and the power-aware SPM architectures.
 
Literatur
1.
Alam M (2008) Reliability- and process-variation aware design of integrated circuits. Microelectronics Reliability 48(8):1114–1122CrossRef
2.
Alam M, Kufluoglu H, Varghese D, Mahapatra S (2007) A comprehensive model for pmos nbti degradation: recent progress. Microelectronics Reliability 47(6):853–862CrossRef
3.
4.
Boning D, Nassif S (1999) Design of high performance microprocessor circuits, In: Models of process variations in device and interconnect, chap 6. IEEE Press
5.
Borkar S (2005) Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25(6):10–16CrossRef
6.
Calimera A, Loghi M, Macii E, Poncino M (2010a) Aging effects of leakage optimizations for caches. In: Proceedings of the Great Lakes symposium on VLSI, pp 95–98
7.
Calimera A, Loghi M, Macii E, Poncino M (2010b) Dynamic indexing: concurrent leakage and aging optimization for caches. In: Proceedings of the ACM/IEEE international symposium on low power electronics and design, pp 343–348
8.
Calimera A, Macii E, Poncino M (2010c) Analysis of nbti-induced snm degradation in power-gated sram cells. In: Proceedings of the IEEE international symposium on circuits and systems, pp 785–788
9.
Calimera A, Loghi M, Macii E, Poncino M (2011) Partitioned cache architectures for reduced nbti-induced aging. In: Proceedings of the conference on design, automation and test in Europe, pp 1 –6
10.
Chen G, Li M, Ang C, Zheng J, Kwong D (2002) Dynamic nbti of p-mos transistors and its impact on mosfet scaling. IEEE Electron Device Lett 23(12):734–736CrossRef
11.
12.
Huard V, Parthasarathy C, Guerin C, Valentin T, Pion E, Planes MMN, Camus L (2008) Nbti degradation: from transistor to SRAM arrays. In: Proceedings of the IEEE annual international reliability physics symposium, pp 289–300
13.
Kandemir M, Irwin M, Chen G, Kolcu I (2004) Banked scratch-pad memory management for reducing leakage energy consumption. In: Proceedings of the ACM/IEEE international conference on computer-aided design, pp 120–124
14.
Kang K, Alam M, Roy K (2007a) Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ. In: Proceedings of the IEEE international test conference, pp 1–10
15.
Kang K, Kufluoglu H, Roy K, Alam MA (2007b) Impact of negative-bias temperature instability in nanoscale sram array: modeling and analysis. IEEE Trans Comput-Aided Des Integr Circuits Syst 26(10):1770–1781CrossRef
16.
Kaxiras S, Hu Z, Martonosi M (2001) Cache decay: exploiting generational behavior to reduce cache leakage power. In: Proceedings of the annual international symposium on computer architecture, pp 240–251
17.
Kim N, Flautner K, Blaauw D, Mudge T (2004) Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans Very Large Scale Integr (VLSI) Syst 12(2):167–184CrossRef
18.
Kumar S, Kim K, Sapatnekar S (2006) Impact of NBTI on SRAM read stability and design for reliability. In: Proceedings of the IEEE international symposium on quality electronic design, pp 213–218
19.
Loghi M, Golubeva O, Macii E, Poncino M (2010) Architectural leakage power minimization of scratchpad memories by application-driven subbanking. IEEE Trans Comput 59(7):891–904CrossRef
20.
Nii K, Makino H, Tujihashi Y, Morishima C, Hayakawa Y, Nunogami H, Arakawa T, Hamano H (1998) A low power sram using auto-backgate-controlled mt-cmos. In: Proceedings of the international symposium on low power electronics and design, pp 293–298
21.
Powell M, Yang SH, Falsafi B, Roy K, Vijaykumar T (2000) Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In: Proceedings of the 2000 international symposium on low power electronics and design, pp 90–95
22.
Ricketts A, Singh J, Ramakrishnan K, Vijaykrishnan N, Pradhan DK (2010) Investigating the impact of NBTI on different power saving cache strategies. In: Proceedings of the conference on design, automation and test in Europe, pp 592–597
23.
Seevinck E, List F, Lohstroh J (1987) Static-noise margin analysis of mos sram cells. IEEE J Solid-State Circuits 22(5):748–754CrossRef
24.
25.
Su C, Despain A (1995) Cache designs for energy efficiency. In: Proceedings of the Hawaii international conference on system sciences, pp 306–315
Metadaten
Titel
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
verfasst von
Cesare Ferri
Dimitra Papagiannopoulou
R. Iris Bahar
Andrea Calimera
Publikationsdatum
01.06.2012
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 3/2012
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-012-5295-2

Weitere Artikel der Ausgabe 3/2012

Journal of Electronic Testing 3/2012 Zur Ausgabe

EditorialNotes

Editorial

OriginalPaper

Diagnostics of Filtered Analog Circuits with Tolerance Based on LS-SVM Using Frequency Features

OriginalPaper

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

OriginalPaper

Digital-Compatible Testing Scheme for Operational Amplifier

OriginalPaper

A New Optimal Test Node Selection Method for Analog Circuit

OriginalPaper

Optimization of SEU Simulations for SRAM Cells Reliability under Radiation

Neuer Inhalt

    Bildnachweise