Novel combined through-wafer-groove fabrication approach and its application in wafer level packaging of GaAs CCD

This paper presents a novel combined through-wafer-groove fabrication approach, which is applied to the wafer level packaging (WLP) of GaAs charge coupled devices (CCD) for electrical interconnection. The combined methodology includes mechanical dicing of the groove and wet chemical etching for polishing. The parameters of the mechanical dicing are researched, including feed speed, dicing directions of the wafer, and cutting depth, to minimize the chipping. Two kinds of chemical solution are tried, and the results are discussed. Besides, the etch rate is measured, which provides a guideline for the process design. Finally, GaAs-CCD WLP sample is achieved and the electrical properties are tested to validate the feasibility of this fabrication approach. This methodology is featured by low cost, low process temperature, and good process uniformity.