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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 6/2010

01.12.2010

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

verfasst von: Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary Carpenter, Kevin Nowka, Jacob A. Abraham

Erschienen in: Journal of Electronic Testing | Ausgabe 6/2010

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Abstract

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.
Vorheriger Artikel Test Technology Newsletter
Nächster Artikel An Effective and Accurate Methodology for the Cell Internal Defect Diagnosis

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Literatur
1.
Abaskharoun N, Hafed M, Roberts GW (2001) Strategies for on-chip sub-nanosecond signal capture and timing measurements. In: International symposium oncircuits and systems, IEEE, pp 174–177
2.
Artisan Components Inc (2002) TSMC 0.18 μm process 1.8 Standard Cell Library Databook
3.
Baker K, Gronthoud G, Lousberg M, Schanstra I, Hawkins C (1999) Defect-based delay testing of resisitive vias-contacts: a critical evaluation. In: International test conference, IEEE, pp 467–476
4.
Balachandran H, Butler KM, Simpson N (2002) Facilitating rapid first silicon debug. In: International test conference, IEEE, pp 628–637
5.
Balajee S, Majhi AK (1998) Automated AC (timing) characterization for digital circuit testing. In: International conference on VLSI design, IEEE, pp 374–377
6.
Bazes M (1985) A novel precision MOS synchronous delay line. IEEE J Solid State Circuits 20(6):1265–1271CrossRef
7.
Bazes M, Ashuri R (1992) A novel CMOS digital clock and data decoder. IEEE J Solid State Circuits 27(12):1934–1940CrossRef
8.
Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V (2003) Parameter variations and impact on circuits and microarchitecture. In: Design automation conference, IEEE, pp 338–342
9.
Bota SA, Rosales M, Rossello JL, Segura J (2006) Low VDD vs. delay: is it really a good correlation metric for nanometer ICs. In: VLSI test symposium, IEEE, pp 358–363
10.
Bowman KA, Duvall SG, Meindl JD (2002) Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J Solid State Circuits 37(2):183–190CrossRef
11.
Cao Y, Sato T, Orshansky M, Sylvester D, Hu C (2000) New paradigm of predictive MOSFET and interconnect modelling for early circuit simulation. In: Custom integrated circuits conference, IEEE, pp 201–204
12.
Chan AH, Roberts GW (2001) A synthesizable fast and high-resolution timing measurement device using a component-invariant vernier delay line. In: International test conference, IEEE, pp 858–867
13.
Chan AH, Roberts GW (2002) A deep sub-micron timing measurement circuit using a single stage vernier delay line. In: Custom integrated circuits conference, IEEE, pp 77–80
14.
Chang JT-Y, Mccluskey EJ (1996) Detecting delay flaws by very-low-voltage testing. In: International test conference, IEEE, pp 367–376
15.
Chen P, Liu S-I, Wu J (1997) A low power high accuracy CMOS time-to-digital converter. In: International symposium on circuits and systems, IEEE, pp 281–284
16.
Chen P, Liu S-I, Wu J (1997) Highly accurate cyclic CMOS time-to-digital converter with extremely low power consumption. IEEE Electron Lett 33(10):858–860CrossRef
17.
Chen P, Liu S-I, Wu J (2000) A CMOS pulse-shrinking delay element for time interval measurement. IEEE Trans Circuits Syst II 47(9):954–958CrossRef
18.
Cheng K-H, Jiang S-Y, Chen Z-S (2003) BIST for clock jitter measurements. In: International symposium on circuits and systems, IEEE, pp V 577–V 580
19.
Christiansen J (1995) An integrated CMOS 0.15ns digital timing generator for TDCs and clock distribution systems. IEEE Trans Nucl Sci 42(4):753–757CrossRef
20.
Dadda L (1965) Some schemes for parallel multipliers. Alta Freq 34:349–356
21.
Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Flautner K, Mudge T (2006) A self-tuning DVS processor using delay-error detection and correction. IEEE J Solid State Circuits 41(4):792–804CrossRef
22.
Datta R, Carpenter G, Nowka K, Abraham JA (2006) A scheme for on-chip timing characterization. In: VLSI test symposium, IEEE, pp 24–29
23.
Datta R, Gupta R, Sebastine A, Abraham JA, Dabreu M (2004) TriScan: a novel DFT technique for CMOS path delay fault testing. In: International test conference, IEEE, pp 1118–1127
24.
Datta R, Sebastine A, Abraham JA (2004) Delay fault testing and silicon debug using scan chains. In: European test symposium, IEEE, pp 46–51
25.
Datta R, Sebastine A, Raghunathan A, Abraham JA (2004) On-chip delay measurement for silicon debug. In: Great lakes symposium on VLSI, ACM, pp 145–148
26.
Dervisoglu B (1999) Design for testability: it is time to deliver it for time-to-market. In: International test conference, IEEE, pp 1102–1111
27.
Dudek P, Szczepanski S, Hatfield JV (2000) A high-resolution CMOS time-to-digital converter utilizing a vernier delay line. IEEE J Solid State Circuits 35(2):240–247CrossRef
28.
Duvall SG (2000) Statistical circuit modeling and optmization. In: International workshop on statistical metrology, IEEE, pp 56–63
29.
Favalli M, Olivo P, Damiani M, Ricco B (1990) Novel design for testability schemes for CMOS IC’s. IEEE J Solid State Circuits 25(5):1239–1246CrossRef
30.
Franco P, McCluskey EJ (1991) Delay testing of digital circuits by output waveform analysis. In: International test conference, IEEE, pp 798–807
31.
Genat J-F (1992) High resolution time-to-digital converter. Nuclear Instruments and Methods in Physics Research, A315
32.
Genat J-F, Rossel F (1988) Ultra high-speed time-to-digital converter. United States Patent no. 4719608
33.
Gorbics MS, Kelly J, Roberts KM, Sumner RL (1997) A high-resolution multihit time-to-digital converter integrated circuit. IEEE Trans Nucl Sci 44(3):379–384CrossRef
34.
Gray CT, Liu W, Noije WAV, Hughes TA, RKC III (1994) A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. IEEE J Solid State Circuits 29(3):340–349CrossRef
35.
Hawkins C, Keshavarzi A, Segura J (2003) A view from the bottom: nanometer technology AC parametric failures—why, where, and how to detect. In: International symposium on defect and fault tolerance, IEEE, pp 267–276
36.
Hsiao M-J, Huang J-R, Yang S-S, Chang T-Y (2001) A built-in timing parametric measurement unit. In: International test conference, IEEE, pp 315–322
37.
Kinra A (1999) Towards reducing functional only fails for the UltraSPARC microprocessors. In: International test conference, IEEE, pp 147–154
38.
Ljuslin C, Christiansen J, Marchioro A, Klingsheim O (1994) An integrated 16-channel CMOS time to digital converter. IEEE Trans Nucl Sci 41(4):1104–1108CrossRef
39.
Maly W, Nigh P (1988) Built-in current testing - feasibility study. In: International conference on computer aided design, IEEE, pp 340–343
40.
Mao W, Ciletti MD (1990) A variable observation time method for testing delay faults. In: Design automation conference, ACM/IEEE, pp 728–731
41.
Maxwell P, Hartanto I, Bentz L (2000) Comparing functional and structural tests. In: International test conference, IEEE, pp 400–407
42.
Miyazaki M, Ono G, Ishibashi K (2002) A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. IEEE J Solid State Circuits 37(2):210–217CrossRef
43.
Naffziger S, Stackhouse B, Grutkowski T (2005) The implementation of a 2-core multi-threaded itanium processor. In: International solid state circuits conference, IEEE, pp 182–184
44.
Nassif SR (2000) Modeling and forecasting of manufacturing variations. In: International workshop on statistical metrology, IEEE, pp 2–10
45.
Needham W, Gollakota N (1996) DFT strategy for intel microprocessors. In: International test conference, IEEE, pp 396–399
46.
Needham et al (1998) High volume microprocessor test escapes, an analysis of defects our tests are missing. In: International test conference, IEEE, pp 25–34
47.
Parvathala P, Maneparambil K, Lindsay W (2002) FRITS - a microprocessor functional BIST method. In: International test conference, IEEE, pp 590–598
48.
Pham D, Asano S, Bolliger M, Day M, Hofstee HP, Johns C, Kahle J, Kameyama A, Keaty J, Masubuchi Y, Riley M, Shippy D, Stasiak D, Suzuoki M, Wang M, Warnock J, Weitzel S, Wendel D, Yamazaki T, Yazawa K (2005) The design and implementation of a first generation CELL processor. In: International solid state circuits conference, IEEE, pp 184–186
49.
Pramanick AK, Reddy SM (1989) On the computation of the ranges of detected delay fault sizes. In: International conference on computer aided design, IEEE, pp 126–129
50.
Raahemifar K, Ahmadi M (2000) Design for testability techniques for detecting delay faults in CMOS/BiCMOS logic families. IEEE Trans Circuits Syst II 47(11):1279–1290CrossRef
51.
Rahkonen T, Kostamovaara J (1990) Pulsewidth measurement using an integrated pulse shrinking delay line. In: International symposium on circuits and systems, IEEE, pp 578–581
52.
Rahkonen T, Kostamovaara J, Saynajakangas S (1988) CMOS ASIC devices for the measurement of short time intervals. In: International symposium on circuits and systems, IEEE, pp 1593–1596
53.
Rahkonen T, Kostamovaara JT (1993) The use of CMOS delay lines for digitization of short time intervals. IEEE J Solid State Circuits 28(8):887–894CrossRef
54.
Rahkonen T, Malo E, Kostamovaara J (1996) A 3V fully integrated digital FM demodulator based on a CMOS pulse-shrinking delay line. In: International symposium on circuits and systems, IEEE, pp 572–575
55.
Raisanen-Ruotsalainen E, Rahkonen T, Kostamovaara J (1995) A low-power CMOS time-to-digital converter. IEEE J Solid State Circuits 30(9):984–990CrossRef
56.
Raychowdhury A, Ghosh S, Bhunia S, Ghosh D, Roy K (2005) A novel delay fault testing methodology using on-chip low overhead delay measurement hardware at strategic test points. In: European test symposium, IEEE, pp 108–113
57.
Sachdev M, Janssen P, Zieren V (1998) Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. In: International test conference, IEEE, pp 204–213
58.
Sasaki O, Taniguchi T, Ohska TK, Mori H, Nonaka T, Kaminishi K, Tsukuda A, Nishimura H, Takeda M, Kawakami Y (1989) 1.2ghz GaAs shift register IC for dead-time-less TDC application. IEEE Trans Nucl Sci 36(1):512–516CrossRef
59.
Savir J (1992) Skewed load transition test: part I, calculus. In: International test conference, IEEE, pp 705–713
60.
Savir J (1992) Skewed load transition test: part II, coverage. In: International test conference, IEEE, pp 714–722
61.
Savir J (1994) On broad-side delay test. In: VLSI test symposium, IEEE, pp 284–290
62.
Segura J, Keshavarzi A, Soden J, Hawkins C (2002) Parametric failures in CMOS ICs - a defect-based analysis. In: International test conference, IEEE, pp 90–99
63.
Silicon Ensemble. Auto place and route tool
64.
Stevens A, Vanberg RP, Spiegel JVD, Williams HH (1989) A Time-to-voltage converter and analog memory for colliding beam detectors. IEEE J Solid State Circuits 24(6):1748–1752CrossRef
65.
Stojanovic V, Oklobdzija V (1999) Comparative analysis of master-slave latches and flip-flops for high-performance and low power systems. IEEE J Solid State Circuits 34(4):536–548CrossRef
66.
Su C, Chen Y-T, Huang M-J, Chen G-N, Lee C-L (2000) All digital built-in delay and crosstalk measurement for on-chip buses. In: Design automation and test in Europe conference and exhibition, IEEE, pp 527–531
67.
Synopsis Inc. Primetime Reference (2000) Version 2000.11
68.
Tam S, Limaye RD, Desai UN (2004) Clock generation and distribution for the 130-nm itanium 2 processor with 6-MB on-die L3 cache. IEEE J Solid State Circuits 39(4):636–642CrossRef
69.
Tisa S, Lotito A, Giudice A, Zappa F (2003) Monolithic time-to-digital converter with 20ps resolution. In: European solid state circuits conference, IEEE, pp 465–468
70.
71.
Vermeulen B, Goel SK (2002) Design for debug: catching design errors in digital chips. IEEE Des Test Comput 19(3):37–45CrossRef
72.
73.
Wood TJ (1999) The test and debug features of the AMD-K7 TM microprocessor. In: International test conference, IEEE, pp 130–136
74.
Wu WC, Lee CL, Wu MS, Chen JE, Abadir MS (2000) Oscillation ring delay test for high performance microprocessors. J Electron Test: Theory Appl 16(1–2):147–155CrossRef
Metadaten
Titel
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
verfasst von
Ramyanshu Datta
Antony Sebastine
Ashwin Raghunathan
Gary Carpenter
Kevin Nowka
Jacob A. Abraham
Publikationsdatum
01.12.2010
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 6/2010
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-010-5188-1

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