Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Bücher
Zeitschriften
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
ATZ-Fachkongress

Chassis.tech plus 2024


4 Kongresse in einer Veranstaltung

Treffen Sie in München die Fachleute von Chassis, Lenkung, Bremsen sowie Reifen/Räder.
Erweiterte Suche
Anmelden
nach oben
The Journal of Supercomputing
Erschienen in: The Journal of Supercomputing 7/2015

01.07.2015

Optimizing the configuration of combined high-radix switches

verfasst von: Juan A. Villar, Francisco J. Andujar, Francisco J. Alfaro, Jose L. Sanchez, Jose Duato

Erschienen in: The Journal of Supercomputing | Ausgabe 7/2015

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Combined high-radix switches are an attractive option for building high-radix switches. The idea basically consists in combining several current smaller single-chip switches to obtain switches that have a greater number of ports. The performance of these kinds of switches varies depending on their internal configuration because the subnetwork interconnecting all the internal switches could become a bottleneck if an inappropriate internal configuration is established. In this paper, we show how to obtain the optimal internal switch configuration by applying a specific methodology. We highlight the impact of internal switch configuration on the network performance by means of case studies.
Vorheriger Artikel Dual-mode inter-router communication channel for deflection-routed networks-on-chip
Nächster Artikel A methodology for speeding up matrix vector multiplication for single/multi-core architectures

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren
Fußnoten
1
We distinguish between network-level connection pattern and SCP. The former is the traditional interconnection pattern connecting switch-based networks (e.g., butterfly permutation in multistage interconnection networks), and the latter refers to how the ports of these kinds of high-radix switches are mapped to the ports of the internal switches.
 
2
In order to identify each type of \(T\)-switch, we are going to use two letters: the first letter identifies the traffic pattern: complement (\(\pi \)), perfect-shuffle (\(\sigma \)), and uniform (\(\upsilon \)) [10]; the second one is used to distinguish the type of \(T\)-switch.
 
3
Pricing from http://​www.​costcentral.​com—$5217 for 24-port QLogic SilverStorm 9024 IBA switch, and $5725 for 36-port QLogic SilverStorm 12200 IBA switch.
 
Literatur
1.
Amiri-Zarandi M, Safaei F, Roozikhar M (2014) Performance evaluation of generic multi-stage interconnection networks with blocking and back-pressure mechanism. J Supercomput 71(3):1–29
2.
Arabnia HR (1995) A distributed stereocorrelation algorithm. In: Proceedings of the 4th international conference on computer communications and networks. IEEE Computer Society, Washington, DC, pp 479–482
3.
Arabnia HR, Oliver MA (1987) A transputer network for the arbitrary rotation of digitised images. Comput J 30(5):425–432CrossRef
4.
Arabnia HR, Oliver MA (1989) A transputer network for fast operations on digitised images. Comput Graph Forum 8(1):3–11CrossRef
5.
Arabnia HR, Smith JW (1993) A reconfigurable interconnection network for imaging operations and its implementation using a multi-stage switching box. In: Proceedings of the 7th international conference on high performance computing: new horizons, pp 349–357
6.
Binkert N, Davis A, Jouppi NP, McLaren M, Muralimanohar N, Schreiber R, Ahn JH (2011) The role of optics in future high radix switch design. In: Proceedings of the 38th annual international symposium on computer architecture. ACM, New York, pp 437–448
7.
Dally W, Hanrahan P, Erez M, Knight T, Labonte F, Ahn JH, Jayasena N, Kapasi U, Das A, Gummaraju J, Buck I (2003) Merrimac: supercomputing with streams. In: Proceedings of the 2003 ACM/IEEE conference on supercomputing, ACM, Phoenix, p 35
8.
Dongarra JJ (2013) Report of the visit to the National University for Defense Technology, Changsha, China
9.
10.
Duato J, Yalamanchili S, Ni L (2003) Interconnection networks. An engineering approach. Morgan Kaufmann Publishers Inc, San Francisco
11.
Eberle H, Garcia PJ, Flich J, Duato J, Drost R, Gura N, Hopkins D, Olesinski W (2008) High-radix crossbar switches enabled by proximity communication. In: Proceedings of the 2008 ACM/IEEE conference on supercomputing. IEEE Press, Austin, pp 1–12
12.
Escudero-Sahuquillo J, García PJ, Quiles FJ, Flich J, Duato J (2013) An effective and feasible congestion management technique for high-performance MINs with tag-based distributed routing. IEEE Trans Parallel Distrib Syst 24(10):1918–1929CrossRef
13.
Escudero-Sahuquillo J, Gran EG, García PJ, Flich J, Skeie T, Lysne O, Quiles FJ, Duato J (2015) Efficient and cost-effective hybrid congestion control for HPC interconnection networks. IEEE Trans Parallel Distrib Syst 26(1):107–119CrossRef
14.
Farouk A, El-Boghdadi HM (2015) A cost-efficient congestion management methodology for fat-trees using traffic pattern detection. J Supercomput 1–28
15.
Gómez C, Gilabert F, Gómez ME, López P, Duato J (2007) Deterministic versus adaptive routing in fat-trees. In: Workshop on communication architecture for clusters. IEEE Press, Los Alamitos, pp 1–8
16.
Gusat M, Abel F, Gramsamer F, Luijten R, Minkenberg C, Verhappen M (2003) Stability degree of switches with finite buffers and non-negligible round-trip time. Int Conf Comput Commun Netw 27(5):243–252
17.
IBA (2007) InfiniBand architecture specification, vol 1. Release 1.2.1
18.
19.
Kim J, Dally WJ, Towles B, Gupta AK (2005) Microarchitecture of a high-radix router. SIGARCH Comput Archit News 33(2):420–431CrossRef
20.
Kim J, Dally WJ, Scott S, Abts D (2008) Technology-driven, highly-scalable dragonfly topology. In: Proceedings of the 35th driven, highly-scalable dragonfly topology. IEEE Computer Society, Washington, DC, pp 77–88
21.
Minkenberg C, Gusat M (2007) Speculative flow control for high-radix datacenter interconnect routers. In: Proceedings of the parallel and distributed processing symposium. IEEE Computer Society, Los Alamitos, pp 1–10
22.
Minkenberg C, Abel F, Muller P, Krishnamurthy R, Gusat M, Hemenway BR (2005) Control path implementation for a low-latency optical HPC switch. In: Proceedings of the 13th symposium on high performance interconnects. IEEE Computer Society, Washington, DC, pp 29–35
23.
Mora G, Flich J, Duato J, López P, Baydal E, Lysne O (2006) Towards an efficient switch architecture for high-radix switches. In: Proceedings of the 2006 ACM/IEEE symposium on architecture for networking and communications systems. ACM, New York, pp 11–20
24.
25.
Petrini F, Vanneschi M (1995) K-ary \(n\)-trees: high performance networks for massively parallel architectures. Tech. Rep. TR-95-18, University of Pisa
26.
Reinemo SA, Sem-Jacobsen FO, Skeie T (2012) Fat-trees and dragonflies–a perspective on topologies. Contributed talk at the HPC Advisory Council Workshop, Lugano
27.
Scott S, Abts D, Kim J, Dally WJ (2006) The BlackWidow high-radix Clos network. SIGARCH Comput Archit News 34(2):16–28CrossRef
28.
29.
Villar JA, Andújar FJ, Sánchez JL, Alfaro FJ, Duato J (2011b) Evaluation of an alternative for increasing switch radix. In: Proceedings of the 10th IEEE international symposium on network computing and applications (NCA), IEEE Computer Society, Washington, DC
30.
Villar JA, Andújar FJ, Sánchez JL, Alfaro FJ, Gámez JA, Duato J (2013) Obtaining the optimal configuration of high-radix combined switches. J Parallel Distrib Comput 73(9):1239–1250CrossRef
31.
Villar JA, Andújar FJ, Alfaro FJ, Sánchez JL, Gámez JA, Duato J (2014) Formalization and configuration methodology for high-radix combined switches. J Supercomput 69(3):1410–1444CrossRef
Metadaten
Titel
Optimizing the configuration of combined high-radix switches
verfasst von
Juan A. Villar
Francisco J. Andujar
Francisco J. Alfaro
Jose L. Sanchez
Jose Duato
Publikationsdatum
01.07.2015
Verlag
Springer US
Erschienen in
The Journal of Supercomputing / Ausgabe 7/2015
Print ISSN: 0920-8542
Elektronische ISSN: 1573-0484
DOI
https://doi.org/10.1007/s11227-015-1408-x

Weitere Artikel der Ausgabe 7/2015

The Journal of Supercomputing 7/2015 Zur Ausgabe

OriginalPaper

A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies

OriginalPaper

A methodology for speeding up matrix vector multiplication for single/multi-core architectures

OriginalPaper

Accelerating MRI reconstruction via three-dimensional dual-dictionary learning using CUDA

OriginalPaper

Dual-mode inter-router communication channel for deflection-routed networks-on-chip

OriginalPaper

Dynamically hierarchical resource-allocation algorithm in cloud computing environment

OriginalPaper

Virtual machine migration in cloud data centers: a review, taxonomy, and open research issues

Premium Partner

    Bildnachweise