Subsecond Annealing of Advanced Materials

From atom bomb simulation to advanced semiconductor processing—what a bellicose-to-peaceful bottom-up approach this research field experienced.

This subchapter presents interesting aspects of pulsed laser annealing. During this process, a laser pulse incorporates heat in the near surface region of a semiconductor or a metal. If the energy density is high enough, the system may melt near the surface. Because of the large temperature gradient, a very fast recrystallization may lead to novel physical material properties. Here we present interesting aspects of the formation of a Mn-rich nanonet in germanium. Important physical phenomena are explained in detail. The material has been fabricated by pulsed laser annealing of Mn implanted Ge wafers with a pulse duration of 300 ns. Due to a segregation instability during recrystallization, Mn segregates at the liquid-solid interface and an approximately 40 nm thick Ge:Mn surface layer is strongly enriched with Mn. Transmission electron microscopy plan-view images reveal a percolating Mn-rich nanonet after etching the top 10 nm surface layer. Hysteretic anomalous Hall effect has been observed up to 30 K, but it vanishes after etching away the 40 nm thick Mn-rich Ge:Mn layer. The nanonet seems to support the correlation between magnetization and hysteretic Hall resistance. Intrinsic charge carrier scattering in the threads or vertices of the Ge:Mn nanonet may lead to the observed anomalous Hall effect. In the outlook the nanonet formation is revealed for supercooled Mn-implanted Si.

The ideal ultrashallow junction relies on (i) high dopant solubility in the crystalline substrate, in order to boost activation and reduce sheet resistance, and (ii) low dopant diffusivity, to facilitate device scaling. Equilibrium solubility is not sufficient to meet the aggressive access resistance targets at advanced device dimensions, thus above-equilibrium metastable solubility must be generated.

A technique to generate such metastable solubilities involves amorphisation of the target silicon substrate, followed by recrystallisation via thermal annealing thereafter. The recrystallisation process is very efficient in placing impurity atoms onto substitutional positions within the semiconductor crystal lattice. The formation of metastable solubility requires care during subsequent processing because further supply of thermal energy, e.g. by back-end processing, causes the metastable condition to revert back to the lower equilibrium state. An approach to control deactivation is by co-implantation of non-dopant species, such as carbon, fluorine, or nitrogen. These species can sink point defects that cause metastable-activation deactivation. Implanting at cryogenic temperatures has also proved successful at reducing defect populations.

Control of diffusion, to facilitate junction and device scaling, can be achieved by reducing the thermal budget of the annealing process. In silicon applications high-temperature millisecond anneals (laser and flash) are popular. Reduced thermal budget via a low-temperature process such as solid-phase-epitaxial-recrystallisation appears to achieve similar results in many regards. Note, anomalous diffusion effects prior, during, and after recrystallisation can be detrimental and cannot be ignored.

In summary, impurity solubilities of group III and V elements in silicon resulting from solid-phase-epitaxial-recrystallisation can beat the maximum equilibrium values by approximately one to two orders of magnitude. This can help reduce parasitic resistances significantly and be of great benefit to the electrical performance of advanced silicon devices.

Heavy doping of semiconductors offers a range of new functionalities that make these materials highly attractive for future information processing technologies like spintronics or quantum computing. Similar to ferromagnetism in diluted magnetic semiconductors it is even possible to achieve a superconducting state in heavily doped elemental semiconductors. Superconductivity in doped semiconductors is of increasing interest for both, fundamental research and applied physics. Herein we report on superconducting germanium layers fabricated by gallium ion implantation and subsequent flash lamp- or rapid thermal annealing.

The intent of the following chapter is to provide a brief introduction of the physics of superconducting semiconductors. It is shown that for these materials it is a key challenge to achieve electrically active dopant concentrations well above the metal insulator transition and at the same time to avoid dopant clustering. In strong contrast to all other doping techniques, ion implantation is not limited to the equilibrium solid solubility of the dopants in the host material. Furthermore, it is widely used in nowadays microelectronics technology which makes this process promising for potential applications.

The microstructure and electrical transport of germanium layers implanted with 2 or 4×10¹⁶ cm⁻² gallium is studied in detail. We extract some information of the influence of gallium rich precipitates that could be formed during ion implantation and subsequent thermal processing on the electrical transport properties. The fabricated layers show p-type conductivity and a charge carrier concentration exceeding the metal insulator transition. This explains a temperature independent resistance in the normal conducting state.

Structural investigations provided by means of Rutherford backscattering spectrometry and transmission electron microscopy reveal distinct differences in the layer morphology depending on the annealing conditions. During flash lamp annealing with a pulse length of 3 milliseconds the layers partly recrystallize via solid phase epitaxy that is stopped by random nucleation and growth leading to a nanocrystalline surface layer. Gallium diffusion and dose loss is clearly suppressed due to the short annealing time. Rapid thermal annealing for 60 seconds provides time enough for a complete solid phase epitaxy. Gallium segregates at the germanium surface during this process. Etching experiments show that the gallium rich regions are responsible for the superconductivity with a critical temperature of 6 K. Therefore, the critical temperature becomes comparable to amorphous gallium films. Based on these findings one can conclude that increasing gallium concentration and thermal budget during annealing lead to gallium segregation which significantly changes the electrical transport and superconducting properties.

SiGe alloys are promising for employment in nano-electronics, infrared photodetectors and next generation of solar cells. The present short review surveys the new field of SiGe transient processing dealing with unusual phase transitions, segregation and structural changes. Fast segregation leads to constitutional supercooling in the melt near the front of crystallization which then results in faceting of the liquid-solid interface followed by generation of extended defects, spatial variation of the composition and formation of nano-cellular structure. Faceting of the interface and formation of cellular structure depends strongly on SiGe alloy composition and on the velocity of melt-solid interface (solidification). Therefore fast processing might become an alternative and very promising pathway for the treatment of SiGe layers and nanostructures. The following issues are shortly reviewed: Segregation of Ge to nanometer-scale cellular network and islands: effect of SiGe composition and crystallization velocity; Morphology and atomic structure of swift heavy ion-induced discontinuous tracks in SiGe alloy layers as a result of fast segregation; Pulsed laser modification of Ge and GeSn nanodots; Laser-induced melting and recrystallization of polycrystalline Ge layer.

The interaction between swift heavy ions (SHI) and a solid has been identified as one of the important physical processes to generate or modify nanostructures in thin solid films. The large part of the energy which is deposited in the electronic subsystem of a material by SHI is known as electronic energy loss and gets coupled to the lattice subsystem in a complex way resulting in a transient (picoseconds to sub-nanosecond) thermal spike within a few nanometer diameter region of the thin solid film along the ion path. The temperature of this narrow zone may raise up to 1000 K or more during this time. This transient heating process is known as lattice thermal spike and can be used as a tool to engineer materials down to the nanoscale. Here we address two important consequences of lattice thermal spike; (i) elongation of metal nanoparticles embedded in dielectric thin films and (ii) generation of a-Si/c-Si nanostructures in a silicon nitride matrix.

(i) Metal nanoparticles embedded in a thin film matrix belong to a class of materials that has potential applications as optical and magnetic sensors, storage, memory devices, field emission display etc. The nanoparticle size and shape, orientation, inter-particle separation and dielectric constant of the surrounding matrix are the crucial parameters which control their properties. Thermal spike generated by SHI in these nanoparticles and surrounding matrix can be used as a unique tool to tailor the shape of the embedded nanoparticles, eventually modifying the physical properties of these materials. Metal nanoparticles, which are mostly spherical in shape in as grown films, get elongated along the direction of SHI due to thermal spike induced melting and stress. After a brief introduction of some fundamental aspects and synthesis of these films, a detailed discussion on elongation of nearly spherical Ni nanoparticles embedded in SiO₂ thin film matrix under 120 MeV Au ion irradiation is made. Various physical parameters influencing the shape modification of nanoparticles under the framework of thermal spike model are discussed.

(ii) a-Si/c-Si nanostructures embedded in different Si-based dielectric matrix have attracted researchers because of their potential application in low-cost Si-based optoelectronic devices. We report here the response of in-situ formed Si-nanostructures embedded in a Si-rich hydrogenated amorphous silicon nitride matrix to 100 MeV Ni⁸⁺ ions irradiation. Si-rich a-SiN _x :H films have been prepared by Hg-sensitized Photo Chemical Vapor Deposition. Presence of elemental Si was confirmed from X-ray photoelectron spectroscopy. Irradiation with a fluence of 5×10¹² ions/cm² under normal incidence at room temperature leads to dissolution of these Si-nanostructures. However, irradiation with a relatively higher fluence of 1×10¹⁴ ions/cm² enhances the nucleation and leads to the formation of amorphous Si-nanostructures in the film. In addition, at the surface a novel effect i.e. partial crystallization of Si-nanostructures along the beam direction is observed. The results are explained on the basis of thermal spike model.

Pulsed-Laser-induced epitaxial growth (PLEG) is an attractive method for lateral overgrowth of orientation-controlled silicon (Si). As underlying MOS-FETs on the seeding crystalline Si wafer is not thermally damaged, the PLEG is promising for monolithic 3D integration of circuits. This paper will review our systematic studies of both simulation and experiment on the PLEG of Si aimed for fundamental understanding of the epitaxial growth and reduction of defect generation. Experimentally a XeCl excimer-laser irradiates the sample which consists of amorphous-silicon (a-Si) deposited on a thick SiO₂ with a small contact opening on a 〈100〉 oriented SOI or bulk-Si wafer. The experiment verified our 2D transient heat transfer simulation results that the combination of the long-pulse and the bulk-Si wafer gives the widest process window. The bulk-Si wafer seeding provided the larger Si island size of 6 μm than that of the SOI (4 μm). From Electron Backscattering Diffraction (EBSD) analysis it was found that 〈100〉 is the main surface crystallographic orientation. However there exist four, isolated secondary sub-grains inside the Si island. TEM cross-sectional image revealed formation of the subgrains due to formation of Σ3 (111) type of coincident site lattice (CSL) boundary originated at the SiO₂ sidewall. We believe that the gentle slope of the side wall allows the extension of the facet to the CSL boundary and subgrains. At last we introduced a way to reduce the CSL boundary formation in the PLEG of Si. By using 75^∘ steep sidewalls of the opening to the seed, we have successfully obtained an array of Si islands having a size of 4 μm with {100} surface orientation only, without any subgrains inside.

The use of laser technologies for the well-defined selective heating of wafers and thin film semiconductors for melt and non-melt rapid thermal processing (RTP) is an alternative way to fulfill the cost and performance goals of the 2nd and 3rd generation of photovoltaic products and other types of thin film electronics as well. A variety of efficient and reliable laser sources are available from UV to IR that can match the absorption characteristics of nearly any material layers and layer stacks. To make technical and economical use of these advantages the laser power has to be focused on the surface with a well-defined beam geometry and intensity profile. For fastest processing of e.g. Gen 5 to Gen 10 solar panels a linear scanning with a line or a rectangular beam profile is needed to achieve the required productivity. In addition to the beam geometry, the intensity distribution in scanning direction is an essential parameter for a controlled temporal heating and cooling profile of the thin film materials.

The constantly decreasing size of semiconductor structures during the 1990’s and early 2000’s led to a reduction of the thermal budget for high temperature activation processes. This reduction was realized by decreasing process duration, coupled with strongly enhanced wafer heating and cooling ramps. Standard lamp technology finally achieved processes as short as a few seconds only with ramps of up to 300 K/s.

The next technology step was achieved when flash lamp annealers and laser devices using continuous wave (cw) lasers were introduced between 2000 and 2005. Flash lamp annealers with their array of high peak power flash lamps can thermally process an entire wafer at once within a period of 1–20 ms. Thus they are able to reduce the process duration by 3 orders of magnitude, compared to standard rapid thermal processing equipment. Annealers using cw lasers shape the laser beam into a narrow line with typical dimensions of 10–20 mm×50–100 μm. To achieve process durations of 1 millisecond or less these lines are scanned across the wafer surface with a velocity of 100–500 mm/s. The semiconductor industry soon began evaluating these tools and started to manufacture devices with 28 nm nodes in mass production.

Other devices, however, require much shorter processes—in the microsecond range or below. These devices are not characterized by even smaller dimensions, but by thermally sensitive structures like metal contacts in close vicinity to the layers which require dopant activation. Localized sub-microsecond processes benefit from the short thermal diffusion length of a few micrometers only which allows keeping nearby structures at reasonably low temperature. In contrast to continuous wave laser annealers for millisecond processes, sub-microsecond activation is realized by using pulsed lasers with pulse durations in the suitable range. In order to achieve high activation rates these processes have to be conducted in the melt regime, where the diffusion rate of impurities in silicon is around seven orders of magnitudes higher than in the solid phase. Examples of devices which benefit greatly from microsecond processes are power transistors like IGBT’s (insulated gate bipolar transistor) and backside illuminated CMOS image sensors which can be found in modern mobile devices like smart phones. Another product range where sub-microsecond processes are presently introduced with technical and commercial success are crystalline solar cells, where localized dopant activation to create so-called selective emitters increases the cell efficiency.

This paper describes how modern electronic devices benefit from sub-microsecond localized thermal processes and explains the demands which processes like IGBT and CMOS sensor backside annealing make. It also describes the laser and optics technology which was developed in order to meet these demands. The laser technology advanced to a level where it can offer additional “free” parameters for process optimization like variable pulse duration, combined with extremely small pulse-to-pulse fluctuations. The duration of a pulsed laser process strongly affects the heat diffusion length and thus the depth of the thermal process. Optical beam parameters like spot size, spot shape and wavelength also allow control of the heat flow and hence better optimization of the thermal processes. The creation of selective emitters of crystalline solar cells using pulsed lasers is a good example to demonstrate how creative optical concepts can help to meet the high throughput demands which the solar cell industry makes.

Flash lamp annealing (FLA), millisecond-order discharge from Xe lamps, can form a few μm-thick polycrystalline Si (poly-Si) films by crystallizing precursor amorphous Si (a-Si) films prepared on low-cost substrates without serious thermal damage onto the whole glass substrates, thanks to its proper annealing duration. The FLA of a-Si films can induce lateral explosive crystallization (EC), self-catalytic crystallization driven by the release of latent heat. Periodic structures with a spacing of ∼1 μm are spontaneously left behind on and inside flash-lamp-crystallized (FLC) poly-Si films formed, when chemical-vapor-deposited (CVD) or sputtered a-Si films are used as precursor films. These microstructures result from the alternative emergence of two types of crystallization with different mechanisms during FLA: one is governed only by solid-phase nucleation (SPN) and the other includes SPN and partial liquid-phase epitaxy (LPE), resulting in the formation of grains with sizes of 10–500 nm. This rapid lateral crystallization leads to the complete preservation of abrupt dopant profiles, which is favorable for device fabrication. This particular crystallization also results in the suppression of hydrogen desorption during FLA, which realizes the formation of poly-Si films with hydrogen atoms on the order of 10²¹/cm³. Hydrogen atoms in poly-Si films probably act to reduce defect density, which can be on the order of 10¹⁶/cm³ after conventional furnace annealing in inert gas atmosphere. These features are suitable for the realization of high-efficiency thin-film poly-Si solar cells. Furthermore, a different type of EC can occur when using electron-beam-(EB-) evaporated a-Si films as precursor films. All the grains in the FLC poly-Si films formed stretch along lateral crystallization direction, and the length of grains is typically more than 10 μm. Based on the results of multi-pulse FLA technique, the velocity of EC is estimated to be ∼14 m/s, which corresponds to the speed of LPE at around the melting point of a-Si, indicating that this EC occurs completely in liquid phase. This approach to form large-grain poly-Si films can also contribute to realizing high-performance solar cells.

The downscaling and stressor technology of Si based devices is extending the performance of the silicon channel to its limits. Further downsizing of CMOS devices below 16 nm will need to solve some of the practical limits caused by one of the integration issues, such as chip performance, cost of development and production, power dissipation, reliability, etc. One solution for the performance progress which can overcome the downsizing limit in silicon technology is the integration of different functional optoelectronic elements within one chip.

We have realized a compact, CMOS compatible and fully integrated solution for the integration of III–V compound semiconductors with silicon technology for optoelectronic applications. The III–V nanostructured semiconductors are synthesized in either silicon or SOI wafers using the combined ion implantation and millisecond flash lamp annealing (FLA) techniques (Prucnal et al. in Nano Lett. 11:2814, 2011). The FLA appears to be the most suitable one for this purpose. The energy budget introduced to the sample during FLA is sufficient to recrystallize silicon amorphized during implantation and to form III–V nanocrystals (NCs). In this paper we will present research results of the microstructural, optical and electrical properties of III–V quantum dots (InAs, GaAs and InP) formed in silicon and on SOI wafers. The influence of the annealing conditions and the lattice mismatch between III–V semiconductors and silicon on the shape of the III–V quantum dots will be examined. The annealing is performed at temperatures by far exceeding the melting point of bulk compound semiconductors, which leads to the formation of III–V nanostructures due to liquid phase epitaxy and enhances the probability for the incorporation of silicon atoms into III–V NCs. Silicon atoms are commonly used as n-type dopants in most III–V semiconductors. Therefore, liquid phase processing leads to the formation of heavily n-type doped single crystalline III–V nanostructures on silicon. If we consider that the synthesized NCs are n-type, by using a p-type silicon substrate a heterojunction can be formed between the III–V NCs and p-type Si. Conventional selective etching has been used to form the n-III–V/p-Si heterojunction. Current-voltage measurements confirm the heterojunction diode formation between n-type III–V quantum dots and p-type Si. The main advantage of our method is its ability to be integrated into large-scale silicon technology, which also allows applying it to Si-based optoelectronic devices.

Short Time Annealing on a microsecond to nanosecond scale presents new challenges to temperature measurement. Pyrometers are widely used owing to their commercial availability, short response time, easy handling and contactless operation. However, they hold a source for considerable measurement errors. False readings are easily gained producing large errors during temperature measurement.

This chapter intends to give the reader an overview on characteristic features associated with Radiation Thermometry in a broader sense and more specifically with Pyrometry.

Over the last decade millisecond annealing (MSA) has made the transition from a research tool to a key manufacturing technology for advanced complementary metal-oxide-semiconductor (CMOS) devices. MSA provides several unique process capabilities that have been very helpful for continued scaling of CMOS. One early application was for improving carrier activation in polysilicon gate electrodes, which reduces carrier depletion effects, providing increased gate capacitance. MSA also enables the formation of highly activated ultra-shallow junctions (USJ), which is essential for controlling short-channel effects while simultaneously minimizing the transistor’s parasitic resistance. New applications have emerged in silicide annealing, especially for NiSi contacts, where MSA can reduce the tendency for dopant deactivation, film agglomeration and for formation of “pipe defects”. As device scaling continues, the need to limit atomic diffusion and defect formation calls for ever-decreasing thermal budget, opening up new opportunities for MSA. Furthermore, the processing has to be compatible with new materials, including high-K dielectrics and metal gates, as well as the features needed for strain engineering and new channel materials. Millisecond annealing is usually performed through the use of pulsed high-power flash-lamps or scanned continuous wave laser beams. The paper describes the relative merits of these approaches, including flash-assisted RTP™ (fRTP™), where rapid wafer preheating is combined with pulsed surface heating to provide great flexibility in the design of thermal profiles. Such flexibility helps optimization in the trade-off between between dopant activation, diffusion, defect annealing and device integration requirements. Another important topic is process control, including issues of wafer temperature measurement and process uniformity. Finally the paper discusses emerging applications for millisecond annealing as a manufacturing technology for new types of semiconductor devices.

In the following chapter, the authors conduct a literature survey of current advances in state-of-the-art low-cost, flexible electronics. A new emerging trend in the design of modern semiconductor devices dedicated to scaling-up, rather than reducing, their dimensions is presented. To realize volume manufacturing, alternative semiconductor materials with superior performance, fabricated by innovative processing methods, are essential. This review provides readers with a general overview of the material and technology evolution in the area of macroelectronics. Herein, the term macroelectronics (MEs) refers to electronic systems that can cover a large area of flexible media. In stark contrast to well-established micro- and nano-scale semiconductor devices, where property improvement is associated with downscaling the dimensions of the functional elements, in macroelectronic systems their overall size defines the ultimate performance (Sun and Rogers in Adv. Mater. 19:1897–1916, 2007). The major challenges of large-scale production are discussed. Particular attention has been focused on describing advanced, short-term heat treatment approaches, which offer a range of advantages compared to conventional annealing methods. There is no doubt that large-area, flexible electronic systems constitute an important research topic for the semiconductor industry. The ability to fabricate highly efficient macroelectronics by inexpensive processes will have a significant impact on a range of diverse technology sectors. A new era “towards semiconductor volume manufacturing…” has begun.

The chapter is organized in three main sections. The candidate materials for flexible, large-area electronics (LAEs) are discussed in Sect. 14.1. Given the limitation of this chapter, only selected groups of the semiconductors are presented. The target materials are Si-based inorganic thin-films and their intriguing, organic competitors. The general attributes of the materials suitable for macroelectronics are revised. The challenges associated with volume manufacturing with emphasis on the evolution of the heating technologies are demonstrated in Sect. 14.2. The final conclusions along with the authors’ considerations on the LAEs’ perspectives are given in Sect. 14.3.

The dilute ferromagnetic semiconductor GaMnAs provides a great promise for its application in spintronics, which combines two degrees of freedom: charge and spin. Mn ions which substitute Ga sublattice sites provide both local magnetic moments and itinerant holes. The magnetic properties of GaMnAs can be controlled by manipulating free carriers via electrical gating. However, the preparation of ferromagnetic GaMnAs presents a big challenge due to the low solubility of Mn in GaAs. To overcome the low solid solubility limit of transition metal dopants in semiconductors, one needs highly nonequilibrium methods to introduce enough dopants and a short-time annealing to activate them. Both ion implantation and pulsed-laser (or flash-lamp) annealing occur far enough from thermodynamic equilibrium conditions. Ion implantation introduces enough dopants. The subsequent short-time annealing deposits energy in the near-surface region to drive a rapid liquid-phase epitaxial growth. Such a nonequilibrium process maintains the supersaturation induced by ion implantation. In this chapter, we review the application of sub-second annealing in the activation of Mn implanted GaAs as well as GaP.