Transactions on Computational Science XXVII

This paper discusses the unusual use of service desk system– tracking of computational tasks on supercomputers as well as the collection of statistical information on the calculations performed. Particular attention is paid to the possibilities of using such statistics by a supercomputer user as well as the data center staff. The analysis of system requirements for tracking computational tasks and capabilities of service desk and job scheduler systems led to design and implementation of a way to integrate these systems to improve computational tasks management.

Reversible arithmetic units such as adders, subtractors and comparators form the essential components of any hardware implementation of quantum algorithms such as Shor’s factoring algorithm. Further, the synthesis methods proposed in the existing literature for reversible circuits target combinational and sequential circuits in general and are not suitable for synthesis of reversible arithmetic units. In this paper, we present several design methodologies for reversible subtractor and reversible adder-subtractor circuits, and a framework for synthesizing reversible arithmetic circuits. Three different design methodologies are proposed for the design of reversible ripple borrow subtractor that vary in terms of optimization of metrics such as ancilla inputs, garbage outputs, quantum cost and delay. The first approach follows the traditional ripple carry approach while the other two use the properties that the subtraction operation can be defined as \(a-b\) = \(\overline{\bar{a}+b}\) and \(a-b\) = \({a+\bar{b}+1}\), respectively. Next, we derive methodologies adapting the subtractor to also perform addition as selected with a control signal. Finally, a new synthesis framework for automatic generation of reversible arithmetic circuits optimizing the metrics of ancilla inputs, garbage outputs, quantum cost and the delay is presented that integrates the various methodologies described in our work.

There are many causes of imbalanced load on a multiprocessor system such as heterogeneity of processors, parallel execution of tasks of varying complexity and also difficulties in estimating complexity of a particular task, however, if one can treat computer as an event-driven processing system and treat tasks as events running through this system the problem of load balance can be reduced to a well-posed mathematical problem which further simplifies to solving a single equation. The load balancer measures both complexity of the task being solved and performance of a computer running this particular task so that a load distribution can be adjusted accordingly. Such load balancer is implemented as a computer program and is known to be able to balance the load on heterogeneous processors in a number of scenarios.

The problem of preservation of stability under discretization is studied. A class of nonlinear switched difference systems is considered. Systems of the class appear as computational schemes for continuous-time switched systems with homogeneous right-hand sides. By using the Lyapunov direct method, some sufficient conditions of the asymptotic stability of solutions for difference systems are obtained. These conditions depend on the information available about the switching law. Three cases are considered. In the first case, we can guarantee the asymptotic stability for any switching law, while in the second and in the third ones, classes of switched signals are determined for which the preservation of the asymptotic stability takes place.

The problem discussed herein is the one of finding the set of stationary points for the Coulomb potential function \( F(P)=\sum _{j=1}^K m_j / |PP_j | \) for the cases of \( K=3 \) and \( K=4 \) positive charges \( \{m_j\}_{j=1}^K \) fixed at the positions \( \{P_j\}_{j=1}^K \subset \mathbb R^2 \). Our approach is based on reducing the problem to that of evaluation of the number of real solution of an appropriate algebraic system of equations. We also investigate the bifurcation picture in the parameter domains.

This work is focused on a number of standard communication patterns of distributed system nodes via messages. Certain characteristics of modern practically applied communication systems are considered. The conclusions are based on the practical development of collective communication strategy processing services and the theoretical basis drawn in the course of testing a number of distributed system prototypes. Development trends of service oriented architecture in the field of interservice communications are considered, including the development tendencies of AMQP and ZMTP protocols.

Problems arising during the design and development of such systems from the horizontal scaling standpoint are specified. The problem of long term control is highlighted in the course of considering issues of data consistency between nodes, availability and partition tolerance. The process of changing workload distribution in a horizontally scaled system is described and issues of fault tolerance of the system in general and its nodes in particular are raised. A way of workload scaling by means of defining an evaluation criterion of node load determined by the system’s business logic and not by the characteristics of the communications level is offered. The efficiency of this approach is shown, with long term control systems used as an example.

We present a digital circuit for restructuring a mesh-connected processor array with faulty processing elements which are directly replaced by spare processing elements located at two orthogonal sides of the array. First, the spare assignment problem is formalized as a matching problem in graph theory. Using the result, we present an algorithm for restructuring the array in a convenient form for finding a matching by a digital circuit. Second, the digital circuit which exactly realizes the algorithm is given. The circuit can be embedded in a target processor array to restructure very quickly the array with faulty processing elements without the aid of a host computer. This implies that the proposed system is effective in not only enhancing the run-time reliability of a processor array but also such an environment that the repair by hand is difficult or a processor array is embedded within a VLSI chip where faulty processor elements cannot be monitored externally through the boundary pins of the chip, and so on. Third, the data about the array reliability considering not only faults in processors but also in that digital circuit are given, and then the effectiveness of our scheme is shown.

This paper presents an encryption based security solution for iris biometric template for secure transmission and database storage. Unlike conventional methods where raw biometric images are encrypted, this paper proposes method for encryption of biometric templates. The advantage of this method is reduced computational complexity as templates are smaller in size than the original biometric image making it suitable for real time applications. To increase the security of the biometric template, encryption is done by using the concept of multiple 1-D chaos and 2-D Arnold chaotic map. The proposed scheme provides a large key space and a high order of resistance against various attacks. Template matching parameters like hamming distance, weighted Euclidean distance, and normalized correlation coefficient are calculated to evaluate the performance of the encryption technique. The proposed algorithm has good key sensitivity, robustness against statistical and differential attacks and an efficient and lossless method for encrypting biometric templates.