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Design Automation for Embedded Systems

Erschienen in:

12.10.2017

TTHLS: an HLS tool for testable hardware generation

verfasst von: S. Ravi, M. Joseph

Erschienen in: Design Automation for Embedded Systems | Ausgabe 3-4/2017

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Abstract

This paper presents a new methodology to incorporate testability to Technology driven high-level synthesis, which is a customized high level synthesis approach based on the target technology. This new methodology called testable technology driven high-level synthesis, generates testable hardware from the corresponding HDL input. Testability incorporation at this higher abstraction, using this integrated approach, proves to be better in terms of area and power consumption than the conventional approaches. The experimental results for the examples considered here prove that the proposed method can reduce up to 9.38% in terms of silicon area and 1.89% in terms of power consumption.

Vorheriger Artikel A novel algorithm for real-time framework in multiprocessor environment

Nächster Artikel An improved low transition test pattern generator for low power applications

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Titel: TTHLS: an HLS tool for testable hardware generation
verfasst von: S. Ravi
M. Joseph
Publikationsdatum: 12.10.2017
Verlag: Springer US
Erschienen in: Design Automation for Embedded Systems / Ausgabe 3-4/2017
Print ISSN: 0929-5585
Elektronische ISSN: 1572-8080
DOI: https://doi.org/10.1007/s10617-017-9192-x

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