VLSI Testing: DFT Strategies and CAD Tools

The increasing complexity of the design primitives used and the higher degree of integration now possible are two factors that impede testability. This is due to the higher number of gates which is not matched by an adequate increase in pin count. Using CAD tools, the cost of designing such “more complicated chips” can of course be kept within reasonable limits, but the cost of test preparation will explode due to the level of complexity. Another fact is that semicustom design is on the increase. Bearing in mind that the intention underlying semicustom design is to achieve low-volume production of a great variety of circuits in a very short turn-around time, it is obvious that the factors of high cost and long test preparation time are becoming more critical, as compared with universal chips produced in large quantities. Thus it is essential to automate test preparation by using adequate CAD tools, such as automatic test pattern generation (ATPG). The basis for the effectiveness of these tools is a strict design for testability (DFT), even if the chip area becomes somewhat larger.