A digital crystal-less clock generator using a phase error corrector

A multi-phase digital crystal-less clock generator (CLCG) with a phase error corrector is presented for on-chip and multi-phase systems. For the temperature variations, the digital temperature compensator (DTC) adjusts the CLCG frequency to achieve the target frequency. The proposed DTC adopts a ring oscillator to detect the frequency drift under the temperature variations. In the trimming process, the supply current controller (SCC) adopts the mutual compensation of threshold voltage and mobility variations to achieve the non-sensitive voltage controlled oscillator (VCO) for temperature variations. The digital CLCG adopts a phase error corrector to calibrate CLCG output phase errors. This digital CLCG output produces the target frequency of 600 MHz and 24 phase outputs, at the 1.2 V supply voltage. The core area of test chip is the 130 × 180 μm² in a 130 nm CMOS process. When the temperature range is from −20 to 80 °C, the frequency accuracies of CLCG are less than ± 60 ppm/°C under the three test chips. The RMS jitter of the period and cycle-to-cycle jitters are 5.3 and 2.4 ps, respectively. The power consumption at 600 MHz is 3.2 mW.