Skip to main content

2020 | OriginalPaper | Buchkapitel

A New Ageing-Aware Approach via Path Isolation

verfasst von : Yue Lu, Shengyu Duan, Tom J. Kazmierski

Erschienen in: Languages, Design Methods, and Tools for Electronic System Design

Verlag: Springer International Publishing

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

NBTI is becoming one of the major circuit reliability issues in nano-scale technologies. BTI can cause a threshold voltage shift in CMOS devices and consequently increase circuit delay. This paper proposed a novel ageing aware approach to improve circuit’s lifetime. The vulnerable circuit paths against ageing effects are isolated. In addition, minimum area overhead is consumed by adopting proposed synthesis algorithm. The simulation results show that the proposed approach can save up to 67.7% area compared with the conventional over-design technique.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Sutaria, K., Ramkumar, A., Zhu, R., Rajveev, R., Ma, Y., & Cao, Y. (2014). BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation. In 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (pp. 1–6). IEEE. Sutaria, K., Ramkumar, A., Zhu, R., Rajveev, R., Ma, Y., & Cao, Y. (2014). BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation. In 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (pp. 1–6). IEEE.
2.
Zurück zum Zitat Duhan, P., Rao, V. R., & Mohapatra, N. R. (2017). PBTI in HKMG nMOS transistors—effect of width, layout, and other technological parameters. IEEE Transactions on Electron Devices, 64(10), 4018–4024.CrossRef Duhan, P., Rao, V. R., & Mohapatra, N. R. (2017). PBTI in HKMG nMOS transistors—effect of width, layout, and other technological parameters. IEEE Transactions on Electron Devices, 64(10), 4018–4024.CrossRef
3.
Zurück zum Zitat Fang, J., & Sapatnekar, S. S. (2013). The impact of BTI variations on timing in digital logic circuits. IEEE Transactions on Device and Materials Reliability 13(1), 277–286.CrossRef Fang, J., & Sapatnekar, S. S. (2013). The impact of BTI variations on timing in digital logic circuits. IEEE Transactions on Device and Materials Reliability 13(1), 277–286.CrossRef
4.
Zurück zum Zitat Kumar, S. V., Kim, C. H., & Sapatnekar, S. S. (2007). NBTI-aware synthesis of digital circuits. In Proceedings of the 44th Annual Design Automation Conference (pp 370–375). ACM. Kumar, S. V., Kim, C. H., & Sapatnekar, S. S. (2007). NBTI-aware synthesis of digital circuits. In Proceedings of the 44th Annual Design Automation Conference (pp 370–375). ACM.
5.
Zurück zum Zitat Wu, K. C., & Marculescu, D. (2009). Joint logic restructuring and pin reordering against NBTI-induced performance degradation. In Proceedings of the Conference on Design, Automation and Test in Europe (pp. 75–80). European Design and Automation Association. Wu, K. C., & Marculescu, D. (2009). Joint logic restructuring and pin reordering against NBTI-induced performance degradation. In Proceedings of the Conference on Design, Automation and Test in Europe (pp. 75–80). European Design and Automation Association.
6.
Zurück zum Zitat Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., & Roy, K. (2007). Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(4), 743–751.CrossRef Paul, B. C., Kang, K., Kufluoglu, H., Alam, M. A., & Roy, K. (2007). Negative bias temperature instability: Estimation and design for improved reliability of nanoscale circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(4), 743–751.CrossRef
7.
Zurück zum Zitat Kang, K., Gangwal, S., Park, S. P., & Roy, K. (2008). NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution? In Proceedings of the 2008 Asia and South Pacific Design Automation Conference (pp. 726–731). IEEE Computer Society Press. Kang, K., Gangwal, S., Park, S. P., & Roy, K. (2008). NBTI induced performance degradation in logic and memory circuits: How effectively can we approach a reliability solution? In Proceedings of the 2008 Asia and South Pacific Design Automation Conference (pp. 726–731). IEEE Computer Society Press.
8.
Zurück zum Zitat Wang, W., Wei, Z., Yang, S., & Cao, Y. (2007). An efficient method to identify critical gates under circuit aging. In IEEE/ACM International Conference on Computer-Aided Design (pp. 735–740). ICCAD 2007. IEEE. Wang, W., Wei, Z., Yang, S., & Cao, Y. (2007). An efficient method to identify critical gates under circuit aging. In IEEE/ACM International Conference on Computer-Aided Design (pp. 735–740). ICCAD 2007. IEEE.
9.
Zurück zum Zitat Wu, K. C., & Marculescu, D. (2011). Aging-aware timing analysis and optimization considering path sensitization. In Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1–6). IEEE. Wu, K. C., & Marculescu, D. (2011). Aging-aware timing analysis and optimization considering path sensitization. In Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1–6). IEEE.
10.
Zurück zum Zitat Chen, X., Wang, Y., Yang, H., Xie, Y., & Cao, Y. (2013). Assessment of circuit optimization techniques under NBTI. IEEE Design & Test 30(6), 40–49.CrossRef Chen, X., Wang, Y., Yang, H., Xie, Y., & Cao, Y. (2013). Assessment of circuit optimization techniques under NBTI. IEEE Design & Test 30(6), 40–49.CrossRef
11.
Zurück zum Zitat Ebrahimi, M., Oboril, F., Kiamehr, S., & Tahoori, M. B. (2013). Aging-aware logic synthesis. In Proceedings of the International Conference on Computer-Aided Design (pp. 61–68). IEEE Press. Ebrahimi, M., Oboril, F., Kiamehr, S., & Tahoori, M. B. (2013). Aging-aware logic synthesis. In Proceedings of the International Conference on Computer-Aided Design (pp. 61–68). IEEE Press.
12.
Zurück zum Zitat Duan, S., Halak, B., & Zwolinski, M. (2017). An ageing-aware digital synthesis approach. In 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (pp. 1–4). IEEE. Duan, S., Halak, B., & Zwolinski, M. (2017). An ageing-aware digital synthesis approach. In 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (pp. 1–4). IEEE.
Metadaten
Titel
A New Ageing-Aware Approach via Path Isolation
verfasst von
Yue Lu
Shengyu Duan
Tom J. Kazmierski
Copyright-Jahr
2020
DOI
https://doi.org/10.1007/978-3-030-31585-6_5

Neuer Inhalt