A power efficient charge pump circuit configuration for fast locking PLL application

One of the vital non-linearity issues that exists in a charge pump (CP) circuit is the current mismatch, which does not only reduce efficiency and increases latency, but also generates phase offset while designing a phase locked loop (PLL) thereby leading to large spurious signals. To mitigate such issues, a new charge pump circuit arrangement incorporating miller Op-Amp is proposed in this paper. The circuit simulation is carried out for 90 nm GPDK (Generic Process Design Kit) technology using Cadence Virtuoso platform at a power supply of 1.2 V. The Op-Amp module consumes a power as small as 85.4 µW after offering a moderate gain of 50.71 dB and input common mode range (ICMR) of − 12.16 mV to 1.1 V. The schematic of proposed CP is found to carry an ‘Up’ and ‘Dn’ current of 11.273 and 10.575 µA respectively to read a current mismatch of as tiny as 0.621%, which gets even reduced to 0.616% in post-layout. The vital attributes of the proposed approach are its fast locking time of 31 ns and power dissipation of 134.1 µW only along with a phase noise and reference spur of − 90.21 dBc/Hz @10 MHz offset and − 80.92 dBc/Hz @10 GHz respectively. The performance metrics are also tested under no skew and 5% process skew at different corners for both schematic and post layout cases to prove the variation awareness and robustness of the circuit. The scalability of this configuration is also validated at lower process nodes such as 28 nm UMC.