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Erschienen in:
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2014 | OriginalPaper | Buchkapitel

2. Continuous-Time Delta-Sigma Modulator

verfasst von : Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Erschienen in: High Speed and Wide Bandwidth Delta-Sigma ADCs

Verlag: Springer International Publishing

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Abstract

This chapter starts with a brief explanation of the operation of an ideal single-loop continuous-time delta-sigma (CTΔΣ) modulator and describes its major building blocks, i.e. the loop filter, quantizer and digital-to-analog converter (DAC). In Sect. 2.2, we introduce the system-level non-idealities that limit the performance of such a modulator. Finally, we will illustrate the effect of system-level non-idealities on the key performance metrics of the modulator: its signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and sampling speed (f s ).

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Vorheriges Kapitel Introduction
Nächstes Kapitel Continuous-Time Delta-Sigma Modulators at High Sampling Rates
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Metadaten
Titel
Continuous-Time Delta-Sigma Modulator
verfasst von
Muhammed Bolatkale
Lucien J. Breems
Kofi A. A. Makinwa
Copyright-Jahr
2014
Buch
High Speed and Wide Bandwidth Delta-Sigma ADCs

Print ISBN: 978-3-319-05839-9

Electronic ISBN: 978-3-319-05840-5

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-3-319-05840-5_2

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