Design and implementation of carry-save adder using quantum-dot cellular automata

Adders are generally made in standard CMOS technology. However, at the nanoscale, CMOS technology faces some issues, such as less control over the gate and high current leakage. Quantum-dot cellular automata (QCA) can be employed to implement the next generation of digital electronic circuits. The present study proposes a carry-save adder (CSA) in QCA technology. The simulation results show the superior performance of the proposed design over the state-of-the-art ripple carry adders, with at least two QCA clocks with faster addition operation even in the worst-case scenario. The proposed QCA-based adder has significantly higher speed and lower energy consumption than its CMOS-based counterpart. The manufacturability of the design is substantially improved. In addition, our proposed full adder requires only 62 cells and the proposed full adder–subtractor requires only 521 cells. The proposed full adder–subtractor occupies 0.62 μm². A design and simulation tool for QCA-based circuits, QCADesigner, is used to analyze the proposed designs.