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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 3/2019

11.05.2019

Design and performance analysis of low-power SRAM based on electrostatically doped tunnel CNTFETs

verfasst von: Shashi Bala, Mamta Khosla

Erschienen in: Journal of Computational Electronics | Ausgabe 3/2019

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Abstract

An electrostatically doped (ED) tunnel carbon nanotube field-effect transistor (CNTFET)-based six-transistor (6T) static random-access memory (SRAM) cell is designed and simulated in HSPICE. The performance of the ED tunnel CNTFET 6T SRAM cell is analyzed based on various figures of merit (FOMs), viz. the read/write noise margin, power dissipation, and read/write delay. Simulation results for the ED tunnel CNTFET-based 6T SRAM are compared with those for a conventional CNTFET-based 6T SRAM cell, revealing that the former shows improved FOMs without losing stability. The read noise margin is improved by 9.2% and 7.5% at VDD of 0.9 V and 0.5 V, while the write noise margin is improved by 16% and 14% at VDD of 0.9 V and 0.5 V, respectively. The power dissipation is reduced by 9 pW at VDD of 0.9 V and by 4 pW at VDD of 0.5 V. The results demonstrate the stability of the proposed ED tunnel CNTFET SRAM for low-power applications.
Vorheriger Artikel An ultra-sensitive gas nanosensor based on asymmetric dual-gate graphene nanoribbon field-effect transistor: proposal and investigation
Nächster Artikel Electrostatically doped drain junctionless transistor for low-power applications

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Metadaten
Titel
Design and performance analysis of low-power SRAM based on electrostatically doped tunnel CNTFETs
verfasst von
Shashi Bala
Mamta Khosla
Publikationsdatum
11.05.2019
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 3/2019
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-019-01345-z

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