Design and realization of high performance logarithmic converters using non-uniform multi-regions constant adder correction schemes

This paper proposes high performance logarithmic converters that use non-uniform multi-regions constant adder correction schemes. Instead of a conventional shift-and-add method, the novel hardware structure presented in this paper uses a constant adder correction circuit that only uses adders. The proposed logarithmic converters can achieve lower approximation error range, smaller hardware area and shorter delay time, which are superior to those of methods previously reported in the literature. The approximation error ranges of the proposed logarithmic converters were 0.0548, 0.0446, 0.032 and 0.0249 for the 3-region, 5-region, 7-region and 9-region constant adder correction logarithmic conversion, respectively. Meanwhile, the proposed converters could achieve 25.63%, 42.47%, 64.43% and 53.23% area delay product savings for the 3-region, 5-region, 7-region and 9-region constant adder correction circuit, respectively. All very large scale integration (VLSI) realization is synthesized using the TSMC 0.18 μm CMOS technology. In addition, the hardware structure of the proposed logarithmic converters is quite simple, with a lower approximation error, fast enough and ROM-free due to the proposed converters only using adders compared to the previously reported shift-and-add based methods. The proposed work can easily realize VLSI digital circuits and is fit for use in embedded digital signal processing and cloud computing.