Emerging Computing: From Devices to Systems

The current decade is poised to see a clear transition of technologies from the de-facto standards. After supporting tremendous growth in speed, density and energy efficiency, newer CMOS technology nodes provide diminishing returns, thereby paving way for newer, non-CMOS technologies. Already multiple such technologies are available commercially to satisfy the requirement of specific market segments. Additionally, researchers have demonstrated multiple system prototypes built out of these technologies, which do co-exist with CMOS technologies. Apart from clearly pushing the limits of performance and energy efficiency, the new technologies present opportunities to extend the architectural limits, e.g., in-memory computing; and computing limits, e.g., quantum computing. The eventual adoption of these technologies are dependent on various challenges in device, circuit, architecture, system levels as well as robust design automation flows. In this chapter, a perspective of these emerging trends is painted in manufacturing technologies, memory technologies and computing technologies. The chapter is concluded with a study on the limits of these technologies.

For decades, humankind has enjoyed the energy efficiency benefits of scaling transistors smaller and smaller, but these benefits are waning. In a worldwide effort to continue improving computing performance, many researchers are exploring a wide range of technology alternatives, ranging from new physics (spin-, magnetic-, tunneling-, and photonic-based devices) to new nanomaterials (carbon nanotubes, two-dimensional materials, superconductors) to new devices (non-volatile embedded memories, ferroelectric-based logic and memories, q-bits) to new systems, architectures, and integration techniques (advanced die- and wafer-stacking, monolithic three-dimensional (3D) integration, on-chip photonic interconnects). However, developing new technologies from the ground up is no simple task, and requires an end-to-end approach addressing many challenges along the way. First of all, a detailed analysis of the overall potential benefits of a new technology is essential; it can take years to bring a new technology to the level of maturity required for high-volume production, and so a team of researchers must ensure upfront that they are developing the right technologies for the right applications. For example, many emerging nanotechnologies are subject to nano-scale imperfections and variations in material properties—how does one overcome these challenges at a very-large scale? Will new design techniques be required? Will circuit and system designers even use the same approaches to designing next generation systems, or would an entirely different approach offer much better results? What level of investment will be required to develop these new technologies, designs, and systems, and at the end of the day, will the outcome be worth the effort? These are just examples of the some of the major questions that are essential to consider as early as possible.

Since the introduction of the transistor, the semiconductor industry has always been able to propose an increasingly higher level of circuit performance while keeping cost constant by scaling the transistor’s area. This scaling process (named Moore’s law) has been followed since the 80s. However, it has been facing new constraints and challenges since 2012. Standard sub-30nm bulk CMOS technologies cannot provide sufficient performance while remaining industrially profitable. Thereby, various solutions, such as FinFETs (Auth et al. 2012) or Fully Depleted Silicon On Insulator (FDSOI) (Faynot et al. 2010) transistors have therefore been proposed. All these solutions enabled Moore’s law scaling to continue. However, when approaching sub-10nm technology nodes, the story starts again. Again, process costs and electrical issues reduce the profitability of such solutions, and new technologies such as Gate-All-Around (GAA) (Sacchetto et al. 2009) transistors are seen as future FinFET replacement candidates.

In the current heterogeneous manycore system regime, the electrical links are not able to provide the bandwidth required by today’s diverse applications while staying within a reasonable power budget. As a result, we need to explore alternate link technologies. In this chapter we provide an overview of three different link technologies—photonic link technology, monolithic 3D link technology, and wireless link technology, which are considered as potential replacements for the electrical link technology. Photonic links use light waves to transmit information, monolithic 3D links use monolithic inter-tier vias for communication between adjacent layers of a 3D system, and wireless links use electromagnetic waves for communication. For each link technology, we first discuss why we should explore that link technology and then provide details about the fundamentals of that link technology.

A digital computing system with ferromagnets as switches, magnetic stray fieds for computation, and domain walls for information transport—is it a curiosity or ready for ultra-large-scale-integration? Over the last decade, starting from sub-micrometer sized Nanomagnets comprised of Co/Pt multilayers, a functionally complete set of logic gates and memory elements were experimentally demonstrated as a potential co-processing unit for CMOS microprocessors called perpendicular Nanomagnetic Logic (pNML). From the beginning of this endeavor, not only single devices but investigations of complex circuits like full-adders and multiplexers finally culminated in an EDA tool called ToPoliNano. It offers a complete design flow for system-level exploration of field coupled technologies, including pNML. In particular, its layout editor MagCAD provides the possibility to design, simulate and re-use pNML modules in larger architectures. The underlying compact models are continuously adapted to newest developments in pNML technology, e.g. improvements in materials, device design and exploitation of novel physical effects. With that, efficient and reliable benchmarking against CMOS implementations is possible, and important system level aspects are directly fed back to the technology and device engineers.

The field of quantum computing is rapidly evolving as it is gradually shifting from curiosity driven research to engineering of Noisy Intermediate Scale Quantum (NISQ) computing devices (Preskill 2018). It is therefore difficult to cover all the developments in a chapter. The intent of this chapter is to introduce quantum computing as a complementary computing machine capable of solving computationally hard problem.

Modern computing systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in computing that cause performance, scalability and energy bottlenecks: (1) data access is a key bottleneck as many important applications are increasingly data-intensive, and memory bandwidth and energy do not scale well, (2) energy consumption is a key limiter in almost all computing platforms, especially server and mobile systems, (3) data movement, especially off-chip to on-chip, is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many technology scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of higher cost. The emergence of 3D-stacked memory plus logic, the adoption of error correcting codes inside the latest DRAM chips, proliferation of different main memory standards and chips, specialized for different purposes (e.g., graphics, low-power, high bandwidth, low latency), and the necessity of designing new solutions to serious reliability and security issues, such as the RowHammer phenomenon, are an evidence of this trend. This chapter discusses recent research that aims to practically enable computation close to data, an approach we call processing-in-memory (PIM). PIM places computation mechanisms in or near where the data is stored (i.e., inside the memory chips, in the logic layer of 3D-stacked memory, or in the memory controllers), so that data movement between the computation units and memory is reduced or eliminated. While the general idea of PIM is not new, we discuss motivating trends in applications as well as memory circuits/technology that greatly exacerbate the need for enabling it in modern computing systems. We examine at least two promising new approaches to designing PIM systems to accelerate important data-intensive applications: (1) processing using memory by exploiting analog operational properties of DRAM chips to perform massively-parallel operations in memory, with low-cost changes, (2) processing near memory by exploiting 3D-stacked memory technology design to provide high memory bandwidth and low memory latency to in-memory logic. In both approaches, we describe and tackle relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, and programming models. Our focus is on the development of in-memory processing designs that can be adopted in real computing platforms at low cost. We conclude by discussing work on solving key challenges to the practical adoption of PIM.

Data converters are ubiquitous in data-abundant mixed-signal systems, where they are heterogeneously distributed across the analog–digital interface. Unfortunately, conventional CMOS data converters trade off speed, power, and accuracy. Therefore, they are exhaustively customized for special purpose applications. Furthermore, intrinsic real-time and post-silicon variations dramatically degrade their performance along with the technology downscaling. Using machine learning techniques and neuromorphic computing, these issues can be overcome. This chapter presents four-bit neuromorphic analog-to-digital (ADC) and digital-to-analog (DAC) converters using memristors that are trained using the stochastic gradient descent algorithm in real-time to autonomously adapt to different design and application specifications, including multiple full-scale voltages, sampling frequencies, number of resolution bits, and quantization scale. Theoretical analysis, as well as simulation results, show the collective resilient properties of our converters in application reconfiguration, logarithmic quantization, mismatches calibration, noise tolerance, and power optimization. Furthermore, large-scale challenges are discussed and solved by leveraging mixed-signal architectures, such as pipelined ADC. These ADC and DAC designs break through the tremendous speed-power-accuracy tradeoff in conventional data converters and enable a general-purpose application architecture with valuable results for neuromorphic computing.

Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This chapter presents a novel framework called SOTERIA that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. With a minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP) our approach can significantly enhance the hardware security in DWDM-based PNoCs.

In this chapter, we introduce the preliminaries of in-memory computing processing-in-memory platforms, such as memristive Memory Processing Units (mMPU), which allow leveraging data locality and performing stateful logic operations. To allow computing of arbitrary Boolean functions using such novel computing platforms, development of design automation flows (EDA) are of critical importance. Typically, EDA flows consist of multiple phases. Technology-independent logic synthesis is the first step, where the input Boolean function is restructured without any specific technology constraints, which is generally followed by a technology-dependent optimization phase, where technology specific hints are used for optimization of the data structure obtained from the first step. The final step is technology mapping, which takes the optimized function representation to implement it using technology-specific constraints. In this chapter, we present an end-to-end mapping framework for mMPU with various mapping objectives. We begin the chapter by presenting an optimal technology mapping method with the goal of mapping a Boolean function on a single row of mMPU. Thereafter, we propose a Look-Up Table (LUT) based mapping that attempts at minimizing delay of mapping, without any area constraints. We extend this method to work with area-constraints. The proposed framework is modular and can be improved with more efficient heuristics as well as technology-specific optimizations. We present benchmarking results with other approaches throughout this chapter.

Reversible computation has received significant attention in recent years as an alternative computation paradigm which can be beneficial e.g. for encoder circuits, low power design, adiabatic circuits, verification—just to name a few examples. Aside from those applications in the design of (conventional) integrated circuits, reversible logic components are also a key ingredient in many quantum algorithms, i.e. in the field of quantum computing which by itself emerged as a very promising computing paradigm that, particularly these days, gains more and more relevance. All that led to a steadily increasing demand for methods that allow for an efficient and correct design of corresponding circuits. Decision diagrams play an important role in the design of conventional circuitry. In the recent years, also their benefits for the design of the newly emerging reversible and quantum logic circuits become evident. In this overview paper, we review and illustrate previous and ongoing work on decision diagrams for such circuits and sketch corresponding design methods relying on them. By this, we demonstrate how broadly decision diagrams can be employed in this area and how they empower the design flow for these emerging technologies.

Quantum computers are built with fragile and noise/error-prone qubits. Some prominent errors include, decoherence/dephasing, gate error, readout error, leakage, and crosstalk. Furthermore, the qubits vary in terms of their quality. Some qubits are healthy whereas others prone to errors. This presents an opportunity to exploit good quality qubits to improve the computation outcome. This chapter reviews the state-of-the-art mapping techniques for error tolerance. We take quantum benchmarks as well as approximate algorithms for applications covering MaxCut, object detection and factorization to illustrate various optimization challenges and opportunities.

The design of reliable wearable systems for real-time and long-term monitoring presents major challenges, although they are poised as the next frontier of innovation in the context of Internet-of-Things (IoT) to provide personalized healthcare. This new generation of biomedical sensors targets to be interconnected in ways that improve our lives and transform the medical industry. Therefore, they offer an excellent opportunity to integrate the next generation of artificial intelligence (AI) based techniques in medical devices. However, several key challenges remain in achieving this potential due to the inherent resource-constrained nature of wearable systems for Big Data medical applications, which need to detect pathologies in real time. Concretely, in this chapter, we discuss the opportunities for edge computing and edge AI in next-generation intelligent biomedical sensors in the IoT era and the key challenges in wearable systems design for pathology detection and health/activity monitoring in the context of IoT technologies. First, we introduce the notion of self-awareness toward the conception of the next-generation intelligent edge biomedical sensors to trade-off machine-learning performance versus system lifetime, according to the application requirements of the medical monitoring systems. Subsequently, we present the implications of personalization and multi-parametric sensing in the context of the system-level architecture of intelligent edge biomedical sensors. Thus, they can adapt to the real world, as living organisms do, to operate efficiently according to the target application requirements and available energy at any moment in time. Then, we discuss the impacts of self-awareness and low-power requirements at the circuit level for sampling through a paradigm shift to react to the input signal itself. Finally, we conclude by highlighting that the techniques discussed in this chapter may be applied jointly to design the next-generation intelligent biomedical sensors and systems in the IoT era.

Reconfigurable computing is an expanding field that, during the last decades, has evolved from a relatively closed community, where hard skilled developers deployed high performance systems, based on their knowledge of the underlying physical system, to an attractive solution to both industry and academia. With this chapter, we explore the different lines of development in the field, namely the need of new tools to shorten the development time, the creation of heterogeneous platforms which couple hardware accelerators with general purpose processors, and the demand to move from general to specific solutions. Starting with the identification of the main limitations that have led to improvements in the field, we explore the emergence of a wide range of Computer Aided Design tools that allow the use of high level languages and guide the user in the whole process of system deployment. This opening to a wider public and their high performance with relatively low power consumption facilitate the spreading in data-centers, where, apart from the undeniable benefits, we have explored critical issues. We conclude with the latest trends in the field such as the use of hardware as a service and the shifting to Domain Specific Architectures based on reconfigurable fabrics.