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Erschienen in: Microsystem Technologies 3/2022

11.09.2018 | Technical Paper

Enhancing digital performance of nanoscale GeOI MOSFETs through optimization of buried oxide properties and channel thickness

verfasst von: Jayanti Paul, Chandrima Mondal, Abhijit Biswas

Erschienen in: Microsystem Technologies | Ausgabe 3/2022

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Abstract

We investigate the effects of thickness as well as dielectric constant of buried oxide on the digital performance of 30 nm germanium-on-insulator (GeOI) MOSFETs employing extensive TCAD simulation. Furthermore the role of Ge channel thickness on various device metrics is studied. For a GeOI pMOSFET having 10-nm thick channel we obtain the lowest value of subthreshold slope, OFF-current, and the highest value of threshold voltage and ON-to-OFF current ratio using 20-nm thick Air as the BOX insulator whereas the lowest intrinsic delay of 5.79 ns is obtained using HfO2 BOX thickness of 200 nm. Moreover, subthreshold slope and OFF-current can further be reduced concurrently improving threshold voltage and ON-to-OFF current ratio by thinning down the channel at the cost of increase in intrinsic delay.

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Literatur
Zurück zum Zitat Abe S, Miyazawa Y, Nakajima Y, Hanajiri T, Toyabe T, Sugano T (2009) Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers. In: Proceedings of the international conference on ultimate integration on silicon, pp 329–332 Abe S, Miyazawa Y, Nakajima Y, Hanajiri T, Toyabe T, Sugano T (2009) Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers. In: Proceedings of the international conference on ultimate integration on silicon, pp 329–332
Zurück zum Zitat ATLAS User’s Manual (2015) A device simulation software package. SILVACO Int, Santa Clara ATLAS User’s Manual (2015) A device simulation software package. SILVACO Int, Santa Clara
Zurück zum Zitat Bedell SW, Majumdar A, Ott JA, Arnold J, Fogel K, Koester SJ, Sadana DK (2008) mobility scaling in short-channel length strained Ge-on-insulator P-MOSFETs. IEEE Electron Device Lett 29(7):811–813CrossRef Bedell SW, Majumdar A, Ott JA, Arnold J, Fogel K, Koester SJ, Sadana DK (2008) mobility scaling in short-channel length strained Ge-on-insulator P-MOSFETs. IEEE Electron Device Lett 29(7):811–813CrossRef
Zurück zum Zitat Chang WH, Irisawa T, Ishii H, Hattori H, Ota H, Takagi H, Kurashima Y, Uchida N, Maeda T (2017) First experimental observation of channel thickness scaling (down to 3 nm) induced mobility enhancement in UTB GeOI nMOSFETs. In: Symposium on VLSI technology digest of technical papers, p 978-4-86348-605-8 Chang WH, Irisawa T, Ishii H, Hattori H, Ota H, Takagi H, Kurashima Y, Uchida N, Maeda T (2017) First experimental observation of channel thickness scaling (down to 3 nm) induced mobility enhancement in UTB GeOI nMOSFETs. In: Symposium on VLSI technology digest of technical papers, p 978-4-86348-605-8
Zurück zum Zitat Daele WVD, Royer CL, Augendre E, Mitard J, Ghibaudo G, Cristoloveanu S (2011) Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs. Solid State Electron 59:25–33CrossRef Daele WVD, Royer CL, Augendre E, Mitard J, Ghibaudo G, Cristoloveanu S (2011) Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs. Solid State Electron 59:25–33CrossRef
Zurück zum Zitat Dal Van et al (2014) Germanium p-channel FinFET fabricated by aspect ratio trapping. IEEE Trans Electron Devices 61(2):430–436CrossRef Dal Van et al (2014) Germanium p-channel FinFET fabricated by aspect ratio trapping. IEEE Trans Electron Devices 61(2):430–436CrossRef
Zurück zum Zitat Ernst T, Tinella C, Raynaud C, Cristoloveanu S (2002) Fringing fields in sub-0.1 lm fully depleted SOI MOSFETs: optimization of the device architecture. Solid State Electron 46:373–378CrossRef Ernst T, Tinella C, Raynaud C, Cristoloveanu S (2002) Fringing fields in sub-0.1 lm fully depleted SOI MOSFETs: optimization of the device architecture. Solid State Electron 46:373–378CrossRef
Zurück zum Zitat Hellings G, Eneman G, Krom R, Jaeger BD, Mitard J, Keersgieter AD, Hoffmann T, Meuris M, Meyer KD (2010) Electrical TCAD simulations of a germanium pMOSFET technology. IEEE Trans Electron Devices 57(10):2539–2546CrossRef Hellings G, Eneman G, Krom R, Jaeger BD, Mitard J, Keersgieter AD, Hoffmann T, Meuris M, Meyer KD (2010) Electrical TCAD simulations of a germanium pMOSFET technology. IEEE Trans Electron Devices 57(10):2539–2546CrossRef
Zurück zum Zitat Hu VP-H, Wu Y-S, Su P (2009) Investigation of electrostatic integrity for ultra-thin-body GeOI MOSFET using analytical solution of Poisson’s equation. Semicond Sci Technol 24:045017-7CrossRef Hu VP-H, Wu Y-S, Su P (2009) Investigation of electrostatic integrity for ultra-thin-body GeOI MOSFET using analytical solution of Poisson’s equation. Semicond Sci Technol 24:045017-7CrossRef
Zurück zum Zitat Hu VP-H, Fan ML, Su P, Chuang CT (2011) Comprehensive analysis of UTB GeOI logic circuits and 6T SRAM cells considering variability and temperature sensitivity. In: IEDM, pp 753–756 Hu VP-H, Fan ML, Su P, Chuang CT (2011) Comprehensive analysis of UTB GeOI logic circuits and 6T SRAM cells considering variability and temperature sensitivity. In: IEDM, pp 753–756
Zurück zum Zitat Hutin L, Royer CL, Damlencourt J-F, Hartmann J-M, Grampeix H, Mazzocchi V, Tabone C, Previtali B, Pouydebasque A, Vinet M, Faynot O (2010) GeOI pMOSFETs scaled down to 30-nm gate length with record off-state current. IEEE Electron Device Lett 31(3):234–236CrossRef Hutin L, Royer CL, Damlencourt J-F, Hartmann J-M, Grampeix H, Mazzocchi V, Tabone C, Previtali B, Pouydebasque A, Vinet M, Faynot O (2010) GeOI pMOSFETs scaled down to 30-nm gate length with record off-state current. IEEE Electron Device Lett 31(3):234–236CrossRef
Zurück zum Zitat Jurczak M, Skotnicki T, Paoli M, Tormen B, Martins J, Regolini JR, Dutartre D, Ribot P, Lenoble D, Pantel R, Monfray S (2000) Silicon-on-nothing (SON)—an innovative process for advanced CMOS. IEEE Trans Electron Devices 47(11):2179–2187CrossRef Jurczak M, Skotnicki T, Paoli M, Tormen B, Martins J, Regolini JR, Dutartre D, Ribot P, Lenoble D, Pantel R, Monfray S (2000) Silicon-on-nothing (SON)—an innovative process for advanced CMOS. IEEE Trans Electron Devices 47(11):2179–2187CrossRef
Zurück zum Zitat Koh R (1999) Buried layer engineering to reduce the drain induced barrier lowering of sub-0.05 µm SOI MOSFET. Jpn J Appl Phys 38:2294–2299CrossRef Koh R (1999) Buried layer engineering to reduce the drain induced barrier lowering of sub-0.05 µm SOI MOSFET. Jpn J Appl Phys 38:2294–2299CrossRef
Zurück zum Zitat Magnone P, Crupi F, Alioto M, Kaczer B, Jaeger BD (2011) Understanding the potential and the limits of germanium pMOSFETs for VLSI circuits from experimental measurements. IEEE Trans VLSI Syst 19(9):1569–1582CrossRef Magnone P, Crupi F, Alioto M, Kaczer B, Jaeger BD (2011) Understanding the potential and the limits of germanium pMOSFETs for VLSI circuits from experimental measurements. IEEE Trans VLSI Syst 19(9):1569–1582CrossRef
Zurück zum Zitat Mitard J et al (2008) Record ION/IOFF performance for 65 nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, CA, pp 1–4 Mitard J et al (2008) Record ION/IOFF performance for 65 nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability. In: Proceedings of IEEE International Electron Devices Meeting, San Francisco, CA, pp 1–4
Zurück zum Zitat Mondal C, Biswas A (2013) 2-D compact model for drain current of fully depleted nanoscale GeOI MOSFETs for improved analog circuit design. IEEE Trans Electron Devices 60(8):2525–2531CrossRef Mondal C, Biswas A (2013) 2-D compact model for drain current of fully depleted nanoscale GeOI MOSFETs for improved analog circuit design. IEEE Trans Electron Devices 60(8):2525–2531CrossRef
Zurück zum Zitat Mondal C, Biswas A (2014) Binary alloy enabled gate work function engineering of nanoscale UTB-GeOI MOSFETs for mixed-signal system-on-chip applications. Superlattices Microstruct 75:118–126CrossRef Mondal C, Biswas A (2014) Binary alloy enabled gate work function engineering of nanoscale UTB-GeOI MOSFETs for mixed-signal system-on-chip applications. Superlattices Microstruct 75:118–126CrossRef
Zurück zum Zitat Ohtou T, Saraya T, Hiramoto T (2008) Variable-body-factor SOI MOSFET with ultrathin buried oxide for adaptive threshold voltage and leakage control. IEEE Trans Electron Devices 55(1):740–742CrossRef Ohtou T, Saraya T, Hiramoto T (2008) Variable-body-factor SOI MOSFET with ultrathin buried oxide for adaptive threshold voltage and leakage control. IEEE Trans Electron Devices 55(1):740–742CrossRef
Zurück zum Zitat Paul BC, Raychowdhury A, Roy K (2005) Device optimization for digital subthreshold logic operation. IEEE Trans Electron Devices 52(2):237–247CrossRef Paul BC, Raychowdhury A, Roy K (2005) Device optimization for digital subthreshold logic operation. IEEE Trans Electron Devices 52(2):237–247CrossRef
Zurück zum Zitat Paul J, Mondal C, Biswas A (2018) Studies of buried oxide properties on nanoscale GeOI pMOSFETs for design of a high performance common source amplifier. Mater Sci Semicond Process 80:85–92CrossRef Paul J, Mondal C, Biswas A (2018) Studies of buried oxide properties on nanoscale GeOI pMOSFETs for design of a high performance common source amplifier. Mater Sci Semicond Process 80:85–92CrossRef
Zurück zum Zitat Pillarisetty et al. (2010) High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture. In: IEDM, pp 150–153 Pillarisetty et al. (2010) High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture. In: IEDM, pp 150–153
Zurück zum Zitat Skotnicki T, Monfray S (2006) Silicon-on-nothing (SON) technology. In: IEDM, p 1-4244-0161-5 Skotnicki T, Monfray S (2006) Silicon-on-nothing (SON) technology. In: IEDM, p 1-4244-0161-5
Zurück zum Zitat Trivedi VP, Fossum JG (2005) Nanoscale FD/SOI CMOS: thick or thin BOX? IEEE Electron Device Lett 26(1):26–28CrossRef Trivedi VP, Fossum JG (2005) Nanoscale FD/SOI CMOS: thick or thin BOX? IEEE Electron Device Lett 26(1):26–28CrossRef
Zurück zum Zitat Van der Steen J-LPJ, Esseni D, Palestri P, Selmi L, Hueting RJE (2007) Validity of the parabolic effective mass approximation in silicon and germanium n-MOSFETs with different crystal orientations. IEEE Trans Electron Devices 54(8):1843–1851CrossRef Van der Steen J-LPJ, Esseni D, Palestri P, Selmi L, Hueting RJE (2007) Validity of the parabolic effective mass approximation in silicon and germanium n-MOSFETs with different crystal orientations. IEEE Trans Electron Devices 54(8):1843–1851CrossRef
Zurück zum Zitat Wang X, Xiang J, Han K, Wang S, Luo J, Zhao C, Ye T, Radamson HH, Simoen E, Wang W (2017) Physically based evaluation of effect of buried oxide. IEEE Trans Electron Devices 64(6):2611–2616CrossRef Wang X, Xiang J, Han K, Wang S, Luo J, Zhao C, Ye T, Radamson HH, Simoen E, Wang W (2017) Physically based evaluation of effect of buried oxide. IEEE Trans Electron Devices 64(6):2611–2616CrossRef
Zurück zum Zitat Wu H, Ye PD (2016) Fully depleted Ge CMOS devices and logic circuits on Si. IEEE Trans Electron Devices 63(8):3028–3035CrossRef Wu H, Ye PD (2016) Fully depleted Ge CMOS devices and logic circuits on Si. IEEE Trans Electron Devices 63(8):3028–3035CrossRef
Zurück zum Zitat Wu Y-S, Hsieh H-Y, Hu VP-H, Su P (2011) Impact of quantum confinement on short-channel effects for ultrathin-body germanium-on-insulator MOSFETs. IEEE Electron Device Lett 32(1):18–20CrossRef Wu Y-S, Hsieh H-Y, Hu VP-H, Su P (2011) Impact of quantum confinement on short-channel effects for ultrathin-body germanium-on-insulator MOSFETs. IEEE Electron Device Lett 32(1):18–20CrossRef
Zurück zum Zitat Yamada T, Abe S, Nakajima Y, Hanajiri T, Toyabe T, Sugano T (2013) Quantitative extraction of electric flux in the buried-oxide layer and investigation of its effects on MOSFET characteristics. IEEE Trans Electron Devices 60(12):3996–4001CrossRef Yamada T, Abe S, Nakajima Y, Hanajiri T, Toyabe T, Sugano T (2013) Quantitative extraction of electric flux in the buried-oxide layer and investigation of its effects on MOSFET characteristics. IEEE Trans Electron Devices 60(12):3996–4001CrossRef
Zurück zum Zitat Yu X, Kang J, Takenaka M, Takagi S (2017) Evaluation of mobility degradation factors and performance improvement of ultrathin-body germanium-on-insulator MOSFETs by GOI thinning using plasma oxidation. IEEE Trans Electron Devices 64(4):1418–1425CrossRef Yu X, Kang J, Takenaka M, Takagi S (2017) Evaluation of mobility degradation factors and performance improvement of ultrathin-body germanium-on-insulator MOSFETs by GOI thinning using plasma oxidation. IEEE Trans Electron Devices 64(4):1418–1425CrossRef
Zurück zum Zitat Zhang R, Huang P, Lin J, Taoka N, Takenaka M, Takagi S (2013) High-mobility Ge p- and n-MOSFETs with 0.7-nm EOT using HfO2/Al2O3/GeOx/Ge gate stacks fabricated by plasma postoxidation. IEEE Trans Electron Devices 60(3):927–934CrossRef Zhang R, Huang P, Lin J, Taoka N, Takenaka M, Takagi S (2013) High-mobility Ge p- and n-MOSFETs with 0.7-nm EOT using HfO2/Al2O3/GeOx/Ge gate stacks fabricated by plasma postoxidation. IEEE Trans Electron Devices 60(3):927–934CrossRef
Metadaten
Titel
Enhancing digital performance of nanoscale GeOI MOSFETs through optimization of buried oxide properties and channel thickness
verfasst von
Jayanti Paul
Chandrima Mondal
Abhijit Biswas
Publikationsdatum
11.09.2018
Verlag
Springer Berlin Heidelberg
Erschienen in
Microsystem Technologies / Ausgabe 3/2022
Print ISSN: 0946-7076
Elektronische ISSN: 1432-1858
DOI
https://doi.org/10.1007/s00542-018-4113-x

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