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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 5/2018

14.09.2018

Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories

verfasst von: Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume

Erschienen in: Journal of Electronic Testing | Ausgabe 5/2018

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Abstract

Novel fault leveling techniques based on address remapping (AR) are proposed in this paper. We can change the logical-to-physical address mapping of the page buffer such that faulty cells within a flash page can be evenly distributed into different codewords. Therefore, the adopted ECC scheme can correct them effectively. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the heuristic fault leveling analysis (FLA) algorithm and evaluating control words used to steer fault leveling. A new page buffer architecture suitable for address remapping is also proposed. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.
Vorheriger Artikel Methodical Approach for Immunity Assessment of Electronic Devices Excited by High Power EMP
Nächster Artikel Impact of Aging on the Reliability of Delay PUFs

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Metadaten
Titel
Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories
verfasst von
Shyue-Kung Lu
Shang-Xiu Zhong
Masaki Hashizume
Publikationsdatum
14.09.2018
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 5/2018
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-018-5752-7

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