Anzeige
Erschienen in:
07.01.2017
High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications
Erschienen in: Journal of Electronic Testing | Ausgabe 1/2017
EinloggenAktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.
Wählen Sie Textabschnitte aus um mit Künstlicher Intelligenz passenden Patente zu finden. powered by
Markieren Sie Textabschnitte, um KI-gestützt weitere passende Inhalte zu finden. powered by
Abstract
Real time high quantity digital data computing design needs to achieve high performance with required accuracy range. The constraints involved with high performance are low power consumption, area efficiency and high speed. This paper proposes a design of high speed energy efficient Static Segment Adder (SSA), which improves the overall performance based on static segmentation. Accuracy Adjustment Logic (AAL) is incorporated to improve the accuracy derived from negating lower order bytes of input operands. In this paper, an integration of static segment method and accuracy adjustment logic is used to achieve computational accuracy for error tolerant applications. The proposed adder design enables to provide high speed and energy efficiency through the static segmentation method. Image enhancement operation is carried out using proposed SSA design. In this method, 99.4% overall computational accuracy for 16-bit addition even with 8-bit adder can be achieved.